• 제목/요약/키워드: metal-semiconductor junction

검색결과 68건 처리시간 0.025초

Effects of metal contacts and doping for high-performance field-effect transistor based on tungsten diselenide (WSe2)

  • Jo, Seo-Hyeon;Park, Jin-Hong
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.294.1-294.1
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    • 2016
  • Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3. The doping level is controlled in the non-degenerate regime, where performance parameters of PPh3 doped WSe2 transistor can be optimized.

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Extension of the Dynamic Range using the Switching Operation of In-Pixel Inverter in Complementary Metal Oxide Semiconductor Image Sensors

  • Seong, Donghyun;Choi, Byoung-Soo;Kim, Sang-Hwan;Lee, Jimin;Lee, Jewon;Lee, Junwoo;Shin, Jang-Kyoo
    • 센서학회지
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    • 제28권2호
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    • pp.71-75
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    • 2019
  • This paper proposes the extension of the dynamic range in complementary metal oxide semiconductor (CMOS) image sensors (CIS) using switching operation of in-pixel inverter. A CMOS inverter is integrated in each unit pixel of the proposed CIS for switching operations. The n+/p-substrate photodiode junction capacitances are added to each unit pixel. When the output voltage of the photodiode is less than half of the power supply voltage of the CMOS inverter, the output voltage of the CMOS inverter changes from 0 V to the power supply voltage. Hence, the output voltage of the CMOS inverter is adjusted by changing the supply voltage of the CMOS inverter. Thus, the switching point is adjusted according to light intensity when the supply voltage of the CMOS inverter changes. Switching operations are then performed because the CMOS inverter is integrated with in each unit pixel. The proposed CIS is composed of a pixel array, multiplexers, shift registers, and biasing circuits. The size of the proposed pixel is $10{\mu}m{\times}10{\mu}m$. The number of pixels is $150(H){\times}220(V)$. The proposed CIS was fabricated using a $0.18{\mu}m$ 1-poly 6-metal CMOS standard process and its characteristics were experimentally analyzed.

광전자소자를 위한 Piezo-Phototronic 효과의 연구 동향 (Recent Advances in the Piezo-Phototronic Effect for Optoelectronics)

  • 신경식;김성수;김도환;윤규철;김상우
    • 한국세라믹학회지
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    • 제50권3호
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    • pp.173-179
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    • 2013
  • Wurtzite nanomaterials, such as ZnO, GaN, and InN, have become a subject of great scientific and technological interest as they simultaneously have piezoelectric and semiconductor properties. In particular, the piezoelectric potential (piezopotential) created by dynamic straining in the nanowires drives a transient flow of current in the external load, converting mechanical energy into electricity. Further, the piezopotential can be used to control the carrier generation, transport, separation, and/or recombination at the metal-semiconductor junction or p-n junction, which is called the piezophototronic effect. This paper reviews the recent advances on the piezophototronic effect to better use the piezophototronic effect to control the carrier generation, transport, separation and/or recombination for improving the performance of optoelectronic devices, such as photon detectors, solar cells and LEDs. This paper also discusses several research and design studies that have improved the output performance of optoelectronic devices.

A 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Ion-Implanted Silicon MESFET's

  • Jit, S.;Morarka, Saurabh;Mishra, Saurabh
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제5권3호
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    • pp.173-181
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    • 2005
  • A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.

SPICE 기반의 발광 다이오드 3차원 회로 모델 (A SPICE-based 3-dimensional circuit model for Light-Emitting Diode)

  • 엄해용;유순재;서종욱
    • 대한전자공학회논문지SD
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    • 제44권2호
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    • pp.7-12
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    • 2007
  • 고휘도 LED(Light-Emitting Diode)를 구현하기 위한 칩 설계의 최적화에 이용할 수 있는 SPICE 기반의 LED 3차원 회로 모델을 개발하였다. 본 모델은 LED를 일정한 면적의 픽셀로 구획하고, 각각의 픽셀은 n-전극, n-형 반도체, p-형 반도체, 및 p-전극 등의 일반적인 LED 레이어 구조를 반영하는 회로망으로 나타낸다. 개별의 박막 층과 접촉 저항은 저항 네트웍으로, pn-접합부는 일반적인 pn-접합 다이오드로 각각 모델링 한다. 별도의 테스트 패턴을 이용하여 독립적으로 추출한 파라미터를 이용한 시뮬레이션 결과는 실험 결과와 정확하게 일치함을 확인하였다.

Thermal Model for Power Converters Based on Thermal Impedance

  • Xu, Yang;Chen, Hao;Lv, Sen;Huang, Feifei;Hu, Zhentao
    • Journal of Power Electronics
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    • 제13권6호
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    • pp.1080-1089
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    • 2013
  • In this paper, the superposition principle of a heat sink temperature rise is verified based on the mathematical model of a plate-fin heat sink with two mounted heat sources. According to this, the distributed coupling thermal impedance matrix for a heat sink with multiple devices is present, and the equations for calculating the device transient junction temperatures are given. Then methods to extract the heat sink thermal impedance matrix and to measure the Epoxy Molding Compound (EMC) surface temperature of the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) instead of the junction temperature or device case temperature are proposed. The new thermal impedance model for the power converters in Switched Reluctance Motor (SRM) drivers is implemented in MATLAB/Simulink. The obtained simulation results are validated with experimental results. Compared with the Finite Element Method (FEM) thermal model and the traditional thermal impedance model, the proposed thermal model can provide a high simulation speed with a high accuracy. Finally, the temperature rise distributions of a power converter with two control strategies, the maximum junction temperature rise, the transient temperature rise characteristics, and the thermal coupling effect are discussed.

전자빔 조사에 의한 반도체 소자의 기능저하 연구 (A Study on Quality Degradation of Semiconductor Devices by Electron Bean Exposure)

  • 조규성;이태훈
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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    • pp.692-696
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    • 1997
  • 본 연구에서는 BJT(Bipolar Junction Transistor)와 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 등을 1MeV에너지의 전자빔을 선량을 변화시켜가며 조사시켜 그 특성 변화를 분석하였다. BJT에 대해서는 조사 전, 후의 전류 이득의 측정을 통해 base 에서의 minority-carrie의 수명 변화에 의해서 전류 이득이 감소하는 것으로 나타났으며, MOSFET의 경우는 oxide 지역의 전하량 변화에 의해서 문턱 전압이 영향을 받음을 확인할 수 있었다. BJT의 minority-carrier의 수명 감소량은 조사 선량이 증가함에 따라 직선적으로 변화함을 알 수 있었고, MOSFET의 문턱 전압의 변화는 nMOS와 pMOS의 경우 서로 다름을 관찰할 수 있었는데 이는 oxide내에서 발생하는 전하에 의해 차이가 남을 알 수 있었다.

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The Electronic Structures and Magnetism of Monolayer Fe on CuGaSe2(001)

  • Jin, Ying-Jiu;Lee, Jae-Il
    • Journal of Magnetics
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    • 제12권2호
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    • pp.59-63
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    • 2007
  • Ferromagnet/Semiconductor heterostructures have attracted much attention because of their potential applications in spintronic devices. We investigated the electronic structures and magnetism of monolayer Fe on $CuGaSe_2(001)$ by using the all-electron full-potential linearized augmented plane-wave method within a generalized gradient approximation. We considered the monolayer Fe deposited on both the CuGa atoms terminated (CuGa-Term) and the Se atom terminated (Se-Term) surfaces of $CuGaSe_2(001)$. The calculated magnetic moment of the Fe atom on the CuGa-Term was about $2.90\;{{\mu}_B}$. Those of the Fe atoms on the Se-Term were in the range of $2.85-2.98\;{{\mu}_B}$. The different magnetic behaviors of the Fe atoms on two different surfaces were discussed using the calculated layer-projected density of states.

Quality Degradation of Semiconductor Transistors by 1MeV Electron Beam Exposure

  • Lee, Tae-Hoon;Gyuseong Cho
    • 한국원자력학회:학술대회논문집
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    • 한국원자력학회 1997년도 춘계학술발표회논문집(2)
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    • pp.401-406
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    • 1997
  • This paper presents preliminary results on the degradation of BJTs(Bipolar Junction Transistors) and MOSFETs(Metal Oxide Semiconductor Field Effect Transistors) by 1MeV electron beam. Exposure experimental results show that the change of minority-carrier life time in base region dominates the behavior of BJTs and that the buildup of charges in oxide region can affect the value of threshold voltage for MOSFETs. It was possible to correlate the decrease of the minority-carrier life time of BJTs with irradiation dose, while the shift of MOSFETs' threshold voltage was not only a function of charge buildup in oxide region.

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HVPE법에 의한 Zn-Doped GaN 박막 제조 (Preparation of Zn-Doped GaN Film by HVPE Method)

  • 김향숙;황진수;정필조
    • 대한화학회지
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    • 제40권3호
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    • pp.167-172
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    • 1996
  • GaN 단결정 박막은 halide vapor phase epitaxy(HVPE)방법을 사용하여 사파이어 기판위에 헤케로에피탁시하게 성장시켰다. 이렇게 제조된 박막은 n형 전동성을 갖는다. 아연(Zn)을 받개 불순물로 도핑시켜 절연형 GaN 박막을 만들었는데 2.64과 2.43eV의 청색영역에서 발광 피크를 가졌다. 본 연구에의해 GaN 박막은 MIS(metal-insulator-semiconductor) 접합구조로 제작이 가능함을 시사하였고, 이종접합형 발광소자 개발에 기초자료가 될 것으로 전망된다.

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