• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 하계종합학술대회 논문집
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• pp.377-379
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• 1989

Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

• 대한전자공학회논문지
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• 제26권7호
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• pp.83-89
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• 1989

강유전성 $PbTiO_3$ 박막을 rf스터링으로 기판온도 $100{\sim}150^{\circ}C$에서 형성시켰다. 이 박막의 구조는 X선 회절결과 비정질 형태로 파이로클로어 구조를 갖고 있었다. 이 박막을 열에 의해 어닐링한 경우는 $550^{\circ}C$에서, 레이저의 주사로 어닐링한 경우는 레이저 출력이 50watts일때 가장 우수한 결정 구조를 구할 수 있었다. 집합에서의 계면 특성을 구하기 위하여 MFS(metal-ferroelectric-semiconductor)및 MFOS(metal-ferroelectric-oxide-semiconductor) 구조를 형성하여 C-V특성을 조사하였다. 이때 MFS보다 MFOS의 경우가 Si표면에 sputter에 의한 결함이 작음을 알 수 있었다.

• 전자통신동향분석
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• 제38권6호
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• 한국정보통신학회논문지
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• 제23권3호
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• pp.311-317
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• 2019

먼저 광학 신호를 이용한 다양한 응용 분야에서의 핵심 요소인 광학 빔 조향 성능 향상을 위하여 실리콘 기반 격자 구조의 특성을 해석하였다. 이를 기반으로 높은 방사 효율과 좁은 빔 폭을 얻기 위해서 기존의 격자 구조 방사기에 분배 브래그 반사기(Distributed Bragg Reflector, DBR)를 집적한 구조를 제안한다. 분배 브래그 반사기의 위치에 따른 방사 효율과 방사 각도의 전치 반폭을 분석하고 이를 토대로 최적화 구조를 제안한다. 제안한 격자 구조는 상보형 금속산화 반도체(complementary metal-oxide semiconductor, CMOS) 공정과 호환 가능하며, 최대 방사 효율 87.1% 및 최소 방사 각도의 반치 전폭 $4.68^{\circ}$를 가진다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.79-82
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• 1998

Film characteristics of thin ONO dielectric layers for MONOS(metal-oxide-nitride-oxide-semiconductor) EEPRM was investigated by AES and AFM. Second derivative spectra of AES Si LVV overlapping peak provided useful information for chemical state analysis of superthin film. The ONO films with dimension of tunneling oxide 24${\AA}$, nitride 33${\AA}$, and blocking oxide 40${\AA}$ were fabricated. During deposition of the LPCVD nitride films on tunneling oxide, this thin oxide was nitrized. When the blocking oxide were deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/O-rich SiON(interface/N-rich SiON(nitride)/-rich SiON(interface)/N-rich SiON(nitride)/O-rich SiON(tunneling oxide).

• ETRI Journal
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• 제37권5호
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• pp.951-960
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• 2015

For a conventional power metal-oxide-semiconductor field-effect transistor (MOSFET), there is a trade-off between specific on-state resistance and breakdown voltage. To overcome this trade-off, a super-junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature-sensing structures-diode and resistive. In this paper, a diode-type temperature-sensing structure for a TMOSFET is designed for a brushless direct current motor with on-resistance of $96m{\Omega}{\cdot}mm^2$. The temperature distribution for an ultra-low on-resistance power MOSFET has been analyzed for various bonding schemes. The multi-bonding and stripe bonding cases show a maximum temperature that is lower than that for the single-bonding case. It is shown that the metal resistance at the source area is non-negligible and should therefore be considered depending on the application for current driving capability.

• Transactions on Electrical and Electronic Materials
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• 제12권5호
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• pp.175-188
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• 2011

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.41-46
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• 2002

In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.