• Journal of Information Display
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• 제9권2호
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• pp.1-4
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• 2008

In this study, we investigate the capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of pentacene, as an organic semiconductor, and polymeric insulators such as poly(4-vinylphenol) (PVP) orpolystyrene (PS) prepared by spin-coating process, to analyze the interfacial characteristics between pentacene and polymeric insulators. Compared with the device with PS, the MIS capacitor with PVP exhibited a pronounced shift in the flat-band voltage according to the bias sweep direction. This hysteric feature in the C-V characteristics is thought to be attributed to the trapped charges at the interface between pentacene and PVP owing to the hydrophilicity of PVP. From the experimental results, we can conclude that surface polarity of polymeric insulator has a critical effect on the interfacial properties, thereby affecting the bias stability of organic thin-film transistors.

• 전기학회논문지
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• 제59권8호
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• pp.1401-1405
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• 2010

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $HfO_2$/p-Si structures. The $HfO_2$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. TEMAHf and $H_2O$ were used as the hafnium and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TEMAHf pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $HfO_2$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.221-224
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• 2000

We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

• ETRI Journal
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• 제17권4호
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• 전기학회논문지
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• 제58권12호
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• pp.2420-2424
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• 2009

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $Al_2O_3/p-Si$ structures. The $Al_2O_3$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. Trimethylaluminum [$Al(CH_3)_3$, TMA] and $H_2O$ were used as the aluminum and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TMA pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $Al_2O_3$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.166.2-166.2
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• 2014

In this work, we demonstrated a facile and effective method for deposition of metal tetraphenylporphyrin (MTPP) thin film by a combined a thermal evaporation (TE) and atomic layer deposition (ALD). For the deposition of Zn-TPP thin film, Tetraphenylporphyrin (TPP) and diethyl zinc (DEZ) were used as organic and inorganic materials, respectively. Optimum conditions for the deposition of Zn-TPP thin film were established systematically: (1) the exposure time of DEZ as inorganic precursor and (2) the substrate temperature were adjusted, respectively. As a result, we verified that the surface reaction between organic semiconductor (TPP) and metal atom (Zn) was ALD process. In addition, we calculated activation energy by using Arrhenius equation for the substrate temperature versus area change rate of pyrrolic nitrogen. The surface and interface reactions between TPP with Zn were investigated by X-ray photoelectron spectroscopy, Raman spectroscopy, UV-vis spectroscopy, and scanning electron microscopy. These results show a facile and well-controllable fabrication technique for the metal-organic thin film for future electronic applications.

• 한국전기전자재료학회논문지
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• 제37권5호
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• pp.507-511
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• 2024

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

• ETRI Journal
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• 제15권2호
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.32-40
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• 2004

An extension of the density-gradient model to include the non-local transport effect is presented. The governing equations can be derived from the first three moments of the Wigner distribution function with some approximations. A new nonlinear discretization scheme is applied to the model to reduce the discretization error. We also developed a new boundary condition for the $Si/SiO_2$ interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. We report the simulation results of a 25-nm metal-oxide-semiconductor field-effect transistor (MOSFET) device.

• Applied Science and Convergence Technology
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• 제26권4호
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• pp.55-61
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• 2017

Graphene, with a carrier mobility achieving up to $140,000cm^2/Vs$ at room temperature, makes it an ideal material for application in semiconductor devices. However, when the metal comes in contact with the graphene sheet, an energy barrier forms at the metal-graphene interface, resulting in a drastic reduction of the carrier mobility of graphene. In this review, the various methods of forming metal-graphene covalent contacts to lower the contact resistance are discussed. Furthermore, the graphene sheet in the area of metal contact can be cut in certain patterns, also discussed in this review, which provides a more efficient approach to forming covalent contacts, ultimately reducing the contact resistance for the realization of high-performance graphene devices.