• Advances in materials Research
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• 제8권4호
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• pp.337-359
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• 2019

Shape Memory Polymer Composites (SMPC) have gained popularity over the last few decades due to its flexible shape memory behaviour over wide range of strains and temperatures. In this paper, non-linear bending analysis has been carried out for SMPC beam under the application of uniformly distributed transverse load (UDL). Simplified C⁰ continuity Finite Element Method (FEM) based on Higher Order Shear Deformation Theory (HSDT) has been adopted for flexural analysis of SMPC. The numerical solutions are obtained by iterative Newton Raphson method. Material properties of SMPC with Shape Memory Polymer (SMP) as matrix and carbon fibre as reinforcements, have been calculated by theory of volume averaging. Effect of temperature on SMPC has been evaluated for numerous parameters for instance number of layers, aspect ratio, boundary conditions, volume fraction of carbon fiber and laminate stacking orientation. Moreover, deflection profile over unit length and behavior of stresses across thickness are also presented to elaborate the effect of glass transition temperature (T_g). Present study provides detailed explanation on effect of different parameters on the bending of SMPC beam for large strain over a broad span of temperature from 273-373K, which encompasses glass transition region of SMPC.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• 한국재료학회지
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• 제13권7호
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• pp.478-483
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• 2003

The crystallographic characteristics of the $(Bi, La)_4$$Ti_3$$O_{12}$ thin film, which is considered as an applicable dielectrics in the ferroelectric RAM device due to a low crystallization temperature and a good fatigue property, were investigated at the atomic scale by high resolution transmission electron microscopy and the high resolution Z-contrast technique. The analysis showed that a (00c) preferred orientation and a crystallization of the film were enhanced with the diffraction intensity increase of the (006) and (008) plane as the annealing temperature increased. It indicated a change of the atomic arrangement in the (00c) plane. Stacking faults on the (00c) plane were also observed. Through the comparison of the high-resolution Z-contrast image and the $Bi_4$$Ti_3$$O_{12}$ atomic model, it was evaluated that the intensity of the Bi atom was different according to the atomic plane, and it was attributed to a substitution of La atom for Bi at the specific atom position.

• 한국전기전자재료학회논문지
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• 제36권3호
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• pp.226-232
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• 2023

As a potential alternative to flash memory, HfO₂/Al₂O₃ stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO₂/Al₂O₃ stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO₂ layer, the memory window of the 5-layered stack increased by 152.4% after O₂ annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO₂/Al₂O₃ stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O₂ and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 1997년도 가을 학술발표회 논문집
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• pp.35-41
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• 1997

Unit cell analyses were peformed to study the engineering properties of satin weave textile composites. Two 5-harness satin weave layers with fiber tow shifts were modeled by unit cells and repeating boundary conditions were applied at the outer surface of the unit cells. Multi-field macroelements were employed to consider the microstructure details and to effectively reduce computer memory requirements. Preliminary results indicated that the engineering properties of 5-harness satin weave textile composites can vary significantly according to the manner how the adjacent fiber tows were arranged in stacking.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• 대한전자공학회논문지SD
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• 제47권11호
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• pp.23-29
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• 2010

메모리칩의 제조 과정에서 발생하는 불량 칩 중 한 두개 비트의 결함이 있는 여러 개의 칩들을 모아서 정상 동작하는 메모리 시스템을 구성하는 방법을 제시한다. 여기에서 제시하는 메모리 시스템은 여러 개의 결함 있는 메모리칩을 겹쳐 쌓은 3차원 다층 구조를 가진다. 이들 칩 간의 신호 선은 through silicon via (TSV)를 통하여 연결한다. 각 칩의 결함이 있는 메모리 셀이 포함된 구역이 칩 마다 서로 다르도록 칩을 분류하여 선택한다. 이 메모리들의 결함이 없는 셀 구역만을 모아 조합하여 전체가 결함이 없는 메모리 시스템이 되도록 한다. 독립적인 주소지정 가능한 n 개의 storage block을 가진 메모리 각각에 k 개의 결함 있는 storage block이 있는 경우 k+1 개의 여유 칩이 조합되어야 한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.540-543
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• 2010

군용 SBC에 주로 사용되는 중앙 처리 장치(Central Processing Unit)는 주로 Power PC의 계열이며 Freescale사의 G4 계열인 74xx 프로세서가 주로 사용된다. 이러한 CPU인 7447A는 System Controller를 통하여 SBC 내의 주 기억 장치와 통신을 한다. 본 논문에서는 위와 같은 SBC의 구조에서 System Controller와 DDR 메모리 소자 간 I/F를 구현함에 있어 PCB적층 구조, 소자들의 Layout, 임피던스매칭과 Rugged 환경 Level에서 적용 되는 군 환경에서 동작 가능한 DDR 메모리를 모듈로 설계하여 구현하였다. 또한, 군용환경에 적용하기위한 SBC의 형상은 주로 6U, 3U의 표준 형태로 설계되어져야 한다.

• 한국재료학회지
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• 제11권2호
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• pp.88-93
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• 2001

$N_2$처리에 의해 Si (001) 기판에 형성된 C49상의 구조를 갖는 에피택셜 $TiSi_2$상의 열적 거동과 결정학적 특성을 X선 회절법 (XRD)과 고분해능 투과전자현미경법 (HRTEM)으로 조사하였다. 에피택결 $C49-TiSi_2$상은 $1000^{\circ}C$ 정도의 고온에서도 안정상인 C54상으로 상변태하지 않고 형태적으로도 고온 특성이 우수하다는 것이 밝혀졌다. HRTEM 결과로부터 에피택결 $TiSi_2$상과 Si 사이의 결정학적 방위관계는 (060) [001]TiSi$_2$//(002) [110]Si임을 알 수 있었고 계면에서의 격자 변형에너지는 misfit 전위의 형성에 의하여 해소되는 것을 확인할 수 있었다. 또한 HRTEM상의 해석과 원자 모델링을 통하여 Si에서 에피택셜 C49-TiSi$_2$상의 형성기구와 C49상의 (020) 면에 존재하는 적층결함을 고찰하였다.

• 한국컴퓨터정보학회논문지
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• 제26권11호
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• pp.1-9
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• 2021

3D-NAND 플래시 메모리는 평면적 구조인 2D-NAND 셀을 적층하는 방식으로 단위 면적당 고용량을 제공한다. 하지만 적층 공정의 특성상 각 레이어별 또는 물리적인 셀 위치에 따라 오류 발생 빈도가 달라질 수 있는 문제가 있다. 이와 같은 현상은 플래시 메모리의 쓰기/지우기(P/E) 횟수가 증가할수록 두드러진다. SSD와 같은 대부분의 플래시 기반 저장장치는 오류 교정을 위하여 ECC를 사용한다. 이 방법은 모든 플래시 메모리 페이지에 대하여 고정된 데이터 보호 강도를 제공하므로 물리적 위치에 따라 오류 발생률이 각기 다르게 나타나는 3D NAND 플래시 메모리에서는 한계를 보인다. 따라서 본 논문에서는 오류 발생률 차이를 보이는 페이지와 레이어를 K-means 머신러닝 알고리즘을 통해 군집으로 분류하고, 각 군집마다 차별화된 데이터 보호강도를 적용한다. 본 논문에서는 페이지와 레이어별로 오류 발생률이 현저하게 달라지는 내구성 테스트가 끝난 시점에서 측정된 오류 발생 횟수를 바탕으로 페이지와 레이어를 분류하고 오류에 취약한 영역에 대해서는 스트라이프에 패리티 데이터를 추가하여 차별화된 데이터 보호 강도 제공을 예시로 보인다. 본 논문에서는 기존의 ECC 또는 RAID 방식의 데이터 보호 구조와 비교하여 제안하는 차별화된 데이터 보호정책이 3D NAND 플래시 메모리의 신뢰성과 수명향상에 기여할 수 있음을 보인다.