• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.269-274
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• 2008

Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.201-208
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• 2016

Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1896-1900
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• 2003

In this paper, a new type of output feedback control, called a receding horizon finite memory control (RHFMC), is proposed for stochastic discrete-time state space systems. Constraints such as linearity and finite memory structure with respect to an input and an output, and unbiasedness from the optimal state feedback control are required in advance. The proposed RHFMC is chosen to minimize an optimal criterion with these constraints. The RHFMC is obtained in an explicit closed form using the output and input information on the recent time interval. It is shown that the RHFMC consists of a receding horizon control and an FIR filter. The stability of the RHFMC is investigated for stochastic systems.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.11
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• pp.972-978
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• 2012

This paper discusses the parallelization of multifrontal solution method, widely used for finite element structural analyses, for a shared memory architecture. Multifrontal method is easier than other linear solution methods because the solution procedure implies that unknowns can be eliminated simultaneously. Two innovative ideas are introduced to achieve optimal solver performance on a shared memory computer. Those are pairing two frontal matrices and splitting the frontal matrix in order to reduce the temporal memory space required by independent computing tasks. Performance comparisons between original algorithm and proposed one prove that proposed method is more computationally efficient on current multicore machines.

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.145-154
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• 2006

This paper improves algorithms of Speculative Partial Redundancy Elimination(SPRE) proposed by Knoop et al. Improving SPRE algorithm performs the execution speed optimization based on the information of the execution frequency from profiling and the memory space optimization. The first purpose of presented algorithm is to reduce in space requirements and the second purpose is to de crease the execution time. Since too much weight on execution speed optimization may cause the explosion of the memory space, it is important to consider the size of memory. This fact can be a big advantage in the embedded system which concerns the required memory size more than the execution speed In this paper we implemented the min-cut algorithm, and this algorithm used the control flow graph is constructed with network and partitioned.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.5
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• pp.931-938
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• 2013

It is hard to extract original data from encrypted data before getting the password in encrypted data with disk encryption software. This encryption key of disk encryption software can be extract by using physical memory analysis. Searching encryption key time in the physical memory increases with the size of memory because it is intended for whole memory. But physical memory data includes a lot of data that is unrelated to encryption keys like system kernel objects and file data. Therefore, it needs the method that extracts valid data for searching keys by analysis. We provide a method that collect only saved memory parts of disk encrypting keys in physical memory by analyzing Windows kernel virtual address space. We demonstrate superiority because the suggested method experimentally reduces more of the encryption key searching space than the existing method.

• Journal of the Korean Institute of Landscape Architecture
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• v.34 no.1 s.114
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• pp.107-119
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• 2006

The Korea Water Resources Corporation(KOWACO) proposed bidding for an alternative design for Hwabuk Multi-purpose Dam in March of 2004. The site is located in Hakseong-ri, Goro-myeon, Gunwi-gun, Gyeongsangbuk-do and has adrainage area of $87.52km^2$. The purpose of this project is to establish an environmentally friendly plan for minimizing the damage that was caused by the construction of the Hwabuk Multi-purpose Dam. The design principle of KOWACO was the restoration of the natural environment, a harmonious landscape, and the creation of a space of regional and local culture. The basic concept of this project involves an ecological-restoration axis and a functional-connection axis. The site is divided into four spaces: (1) the space of memory and symbol, (2) the space of nature and ecology, (3) the space of regional and local culture, and (4) the space of the regional economy. There are four sub-spaces in the space of memory and symbol: the track forest, the time forest, the memory room, and the sun plaza. There are three sub-spaces in the space of nature and ecology: the habitat of aquatic birds, the wind forest, and the eco-corridor. There are five themed parks in the space of regional and local culture: the culture and relic room, the wildflower garden, the ecological pond, the insect observation park, and the pyogo maze. There are three areas in the space of the regional economy: the forest pension, the waterside pension, and the community center, as Dungdungi village was reorganized to serve as a lodging complex. These themed parks, working together, can offer an effective space for nature, culture, rest, and experience.

• Journal of Space Technology and Applications
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• v.1 no.2
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• pp.256-267
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• 2021

In this paper, the New Space characteristics and response of micro & small satellite, and space industrialization strategy using domestic technologies are described. Recently, micro & small satellites are developed worldwide, including Starlink, having the characteristics of low-cost, light-weight and satellite constellation. Therefore, it is necessary to prepare for the constellation operation by considering the use of Commercial Off-The-Shelf (COTS) parts, satellite weight, shape and mass production. In particular, it is necessary to develop Multi Input Multi Output (MIMO) technology in consideration of the frequency interference during constellation operation, and to prepare and make efforts to secure frequencies in the government. Among the commercial-grade memories of Samsung Electronics and SK Hynix, the space-grade memory field using radiation tolerant memory and the high reliable packaging and space environment test technology has potential as a space industrialization strategy.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.4
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• pp.187-194
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• 2018

The operating system for IoT should have a small memory footprint and provide low power state, real-time, multitasking, various network protocols, and security. Although the Zephyr kernel, an operating system for IoT, released by the Linux Foundation in February 2016, has these features but errors generated by the user code can generate fatal problems in the system because the Zephyr kernel adopts a single-space method that both the user code and kernel code execute in the same space. In this research, we propose a space separation method, which separates kernel space and user space, to solve this problem. The space separation that we propose consists of three modifications in Zephyr kernel. The first is the code separation that kernel code and user code execute in each space while using different stacks. The second is the kernel space protection that generates an exception by using the MPU (Memory Protection Unit) when the user code accesses the kernel space. The third is the SVC based system call that executes the system call using the SVC instruction that generates the exception. In this research, we implemented the space separation in Zephyr v1.8.0 and evaluated safety through abnormal execution of the user code. As the result, the kernel was not crashed by the errors generated by the user code and was normally executed.