• 전기전자학회논문지
• /
• 제27권4호
• /
• pp.386-390
• /
• 2023

본 연구에서는 기존 상보성 금속 산화막 반도체 공정을 활용하여 제작된 실리콘 나노시트(SiNS) 피드백 전계효과 트랜지스터(FBFET)의 준비휘발성 메모리 특성을 분석하였다. 과노광공정을 이용하여 형성된 SiNS 채널층의 폭은 180 nm이고 높이는 70 nm이었다. 양성 피드백 루프를 기반으로 동작하는 SiNS FBFET의 낮은 문턱전압이하 기울기는 1.1 mV/dec, ON/OFF 전류비는 2.4×10⁷이었다. 또한 SiNS FBFET는 50 초 동안 상태를 유지하는 메모리 특성을 보여 준휘발성메모리 소자로 활용 가능성을 제시하였다.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 2007년도 춘계학술대회 학술발표 논문집 제17권 제1호
• /
• pp.485-488
• /
• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.

• 전자공학회논문지A
• /
• 제32A권10호
• /
• pp.81-92
• /
• 1995

In this paper, we present a high-level synthesis system that generates area-efficient RT-level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. Experimental results show the effectiveness of the proposed algorithm. When compared with previous approaches for several benchmarks available from literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.26-31
• /
• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.199-202
• /
• 2004

NFGM(Nano-Floating Gate Memory) is a very prospective candidate memory for the next generation with MRAM, PRAM, PoRAM. Among these memory devices for the next generation, NFGM has a lot of merits such as a simple low cost fabrication process, improved retention time, lower operating voltages, high speed program/erase time and so on. Therefore, many intensive researches for NFGM have been performed to improve device performance and reliability, which depends on the ability to control particle size, size distribution, crystallity, areal particle density and tunneling oxide quality. In this paper, we investigate the researches for NFGM up to recently.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
• /
• pp.80-81
• /
• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• 한국전기전자재료학회논문지
• /
• 제16권5호
• /
• pp.372-377
• /
• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• 한국산업융합학회 논문집
• /
• 제24권1호
• /
• pp.69-77
• /
• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• 전자통신동향분석
• /
• 제38권5호
• /
• pp.23-33
• /
• 2023

With the widespread demand from data-intensive tasks such as machine learning and large-scale databases, the amount of data processed in modern computing systems is increasing exponentially. Such data-intensive tasks require large amounts of memory to rapidly process and analyze massive data. However, existing computing system architectures face challenges when building large-scale memory owing to various structural issues such as CPU specifications. Moreover, large-scale memory may cause problems including memory overprovisioning. The Compute Express Link (CXL) allows computing nodes to use large amounts of memory while mitigating related problems. Hence, CXL is attracting great attention in industry and academia. We describe the overarching concepts underlying CXL and explore recent research trends in this technology.

• 대한간호학회지
• /
• 제30권5호
• /
• pp.1170-1180
• /
• 2000

This study was a quasi-experimental study to confirm the effects of a memory training program using efficacy sources. The purpose was to develop an effective memory training program for elderly people and to identify the effects of the memory training program. This study was carried out between February 24 and July 18, 1999 and the subjects of the study were 102 elderly people who were participants at a welfare institute in Seoul. The experimental group (51) and the control group (51) were assigned by means of participation order. The control group was matched to the experimental group and was selected considering age, sex, and religion. The experimental group participated in the memory training program. The memory training program was based on the literature of Fogler & Stern (1994), Wang & Lee (1990), Lee (1991) and Lee (1993). The memory training program was given twice a week for two weeks with each program lasting two hours. Task centered memory self-efficacy was measured using the Memory Self-Efficacy Scale developed by Berry & Dennehey (1989) and Meta Memory was measured by the MIA developed by Dixon et al. (1988) Memory performance was measured by the word list developed by Cho Sung Won (1995) and the face recognition task (Face Recognition Task developed for this study). Data were analyzed by SPSS PC and the results are described below. 1. The experimental group which participated in the Memory Training Program showed higher task centered memory self-efficacy scores as compared to the control group (t=4.354, P=.0001). 2. The experimental group which participated in the Memory Training Program showed higher metamemory scores as compared to the control group (t=4.733, P=.0001). 3. The experimental group which participated in the Memory Training Program showed higher memory performance scores as compared to the control group (t=7.500, P=.0001). The memory performance involved an immediate word recall task, a delayed word recall task, a word recognition task, and the face recognition task. 4. In the experimental group, there was significant correlation between the task centered memory self-efficacy scores and the metamemory scores (r=.382, P=.006), but the correlation between the task centered memory self-efficacy scores and the memory performance scores and between the metamemory scores and the memory performance scores were not significant. The results showed that task centered memory self-efficacy, meta memory and memory performance improved following the Memory Training Program including the memory process, changes in memory with aging, and appropriate use of memory strategies. Memory Training Program is an effective nursing intervention for improving memory in elderly people and, also, in people with complaints of memory loss.