• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.21 no.2
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• pp.283-294
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• 2023

APro, developed in KAERI for the process-based total system performance assessment (TSPA) of deep geological disposal systems, performs finite element method (FEM)-based multiphysics analysis. In the FEM-based analysis, the mesh element quality influences the numerical solution accuracy, memory requirement, and computation time. Therefore, an appropriate mesh structure should be constructed before the mesh stability analysis to achieve an accurate and efficient process-based TSPA. A generic reference case of DECOVALEX-2023 Task F, which has been proposed for simulating stationary groundwater flow and time-dependent conservative transport of two tracers, was used in this study for mesh stability analysis. The relative differences in tracer concentration varying mesh structures were determined by comparing with the results for the finest mesh structure. For calculation efficiency, the memory requirements and computation time were compared. Based on the mesh stability analysis, an approach based on adaptive mesh refinement was developed to resolve the error in the early stage of the simulation time-period. It was observed that the relative difference in the tracer concentration significantly decreased with high calculation efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• Journal of KIISE
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• v.44 no.6
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• pp.607-612
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• 2017

This paper presents an attempt to apply Deep Learning technology to solve the problem of forecasting floods in urban areas. We employ Recurrent Neural Networks (RNNs), which are suitable for analyzing time series data, to learn observed data of river water and to predict the water level. To test the model, we use water observation data of a station in the Trinity river, Texas, the U.S., with data from 2013 to 2015 for training and data in 2016 for testing. Input of the neural networks is a 16-record-length sequence of 15-minute-interval time-series data, and output is the predicted value of the water level at the next 30 minutes and 60 minutes. In the experiment, we compare three Deep Learning models including standard RNN, RNN trained with Back Propagation Through Time (RNN-BPTT), and Long Short-Term Memory (LSTM). The prediction quality of LSTM can obtain Nash Efficiency exceeding 0.98, while the standard RNN and RNN-BPTT also provide very high accuracy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.11
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• pp.1220-1228
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• 2010

In this paper, we suggest a scheme to develop an efficient discrete nonlinear model based on polynomial structure for a RF power amplifier(PA). We describe a procedure to extract a discrete nonlinear model such as Taylor series or memory polynomial by sampling the input and output signal of RF PA. The performance of the model is analyzed varying the model parameters such as sample rate, nonlinear order, and memory depth. The results show that the relative error of the model is converged if the parameters are larger than specific values. We suggest an efficient modeling scheme considering complexity of the discrete model depending on the values of the model parameters. Modeling efficiency index(MEI) is defined, and it is used to extract optimum values for the model parameters. The suggested scheme is applied to discrete modeling of various RF PAs with various input signals such as WCDMA, WiBro, etc. The suggested scheme can be applied to the efficient design of digital predistorter for the wideband transmitter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Journal of the Korean Magnetics Society
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• v.18 no.3
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• pp.103-108
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• 2008

Magnetoresistive random access memory (MRAM) don't get very public face on the field of non-volatile memory. Because recording capacity of MRAM is smaller than other non-volatile memory and structurally, magnetic efficiency of MRAM is very bad. We diminish a size of one cell in order to make MRAM of high recording capacity. But It don't make high recording field in general structures consisting of two current wire. Accordingly, We make a cell of small size is impossible. In this paper, we suggest new MRAM that it have two pole of high permeability on both ends of recording layer. Because magnetic efficiency of new MRAM is higher than exiting MRAM, it can make high recording field. And we can diminish the size of one cell due to recording layer of high coercivity. We used three-dimension finite element method to prove the reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.

• Korean Journal of Remote Sensing
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• v.22 no.6
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• pp.601-612
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• 2006

This study proposes RAG (Region Adjancency Graph)-based image segmentation for large imagery in remote sensing. The proposed algorithm uses CN-chain linking for computational efficiency and multi-window operation of sliding structure for memory efficiency. Region-merging due to RAG is a process to find an edge of the best merge and update the graph according to the merge. The CN-chain linking constructs a chain of the closest neighbors and finds the edge for merging two adjacent regions. It makes the computation time increase as much as an exact multiple in the increasement of image size. An RNV (Regional Neighbor Vector) is used to update the RAG according to the change in image configuration due to merging at each step. The analysis of large images requires an enormous amount of computational memory. The proposed sliding multi-window operation with horizontal structure considerably the memory capacity required for the analysis and then make it possible to apply the RAG-based segmentation for very large images. In this study, the proposed algorithm has been extensively evaluated using simulated images and the results have shown its potentiality for the application of remotely-sensed imagery.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of Digital Contents Society
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• v.16 no.4
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• pp.535-543
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• 2015

Recently, NAND flash based storage devices are being used as a storage device in various fields through hiding the limitations of NAND flash memory and maximizing the advantages. In particular, those storage devices contain a software layer called Flash Translation Layer(FTL) to hide the "erase-before-write" characteristics of NAND flash memory. FTL includes the metadata for managing the data requested from host. That metadata is stored in internal memory because metadata is very frequently accessed data for processing the requests from host. Thus, if the power-loss occurs, all data in memory is lost. So metadata management scheme is necessary to store the metadata periodically and to load the metadata in the initialization step. Therefore we proposed the scheme which satisfies the core requirements for metadata management and efficient operation. And we verified the efficiency of proposed scheme by experiments.