• 제목/요약/키워드: memory characteristics

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SDF 알고리즘을 이용한 연상기억 처리모델 (A new associative memory model using SDF filter)

  • 정재우
    • 한국광학회:학술대회논문집
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    • 한국광학회 1989년도 제4회 파동 및 레이저 학술발표회 4th Conference on Waves and lasers 논문집 - 한국광학회
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    • pp.95-98
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    • 1989
  • A new associative memory model using the SDF filter, one of the multiple filter for pattern recognition, is suggested in this paper. The SDF filter characteristics such as pattern classification lets the memorized patterns have orthogonal characteristics one another, so that enhances the associative memory's retrieval ability to the original pattern. The computer simulation shows that this new model is very useful in case that the imput patterns are seriously distorted and the cross-correlation between the memorized patterns is very high.

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압축 하중사이클을 이용한 양방향 형상기억효과 특성 연구 (Experimental Study on the TWSME Characteristics using Compressive Loading Cycles)

  • 유영익;김현철;이정주;이우용
    • 한국자동차공학회논문집
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    • 제17권4호
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    • pp.101-107
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    • 2009
  • Actuators using shape memory alloys use the one-way shape recovery stress. But when external load is applied the accumulated plastic strain induced by repeated deformation is the factor of generation of uncorrect recovery stress and unreliability. To solve this problem, two-way shape memory effect (TWSME) is considered. TWSME induced by plastic deformation have advantages including simple heating cycle without external force and enough recovery force for using actuators. but there is no research on cylinder-type or tube-type shape memory alloy actuators using two-way shape memory effect until now. Therefore in this study, characteristics of two-way shape memory effect is verified through the compression experiments using cylinder-type and tube-type specimens.

저전압 EEPROM을 위한 Scaled MONOS 비휘발성 기억소자의 제작 및 특성에 관한 연구 (A study on the fabrication and characteristics of the scaled MONOS nonvolatile memory devices for low voltage EEPROMs)

  • 이상배;이상은;서광열
    • E2M - 전기 전자와 첨단 소재
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    • 제8권6호
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    • pp.727-736
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    • 1995
  • This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

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대전입자형 디스플레이 소자의 점유면적 평가방법에 의한 구동특성 및 메모리 효과 분석 (Analysis of Driving Characteristics and Memory Effect by Occupation Area Evaluation Method of Charged Particle Type Display Device)

  • 김진선;김영조
    • 한국전기전자재료학회논문지
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    • 제24권8호
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    • pp.669-673
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    • 2011
  • The charged particle type display is a kind of the reflectivity type display and shows an image by absorption and reflection of external light source, which has keep an image without additional electric power because of bistability. In this paper, we made a device whose cell gap is $56\;{\mu}m$ and also analyzed driving and memory characteristics by applied driving voltages. As a result, we found that the driving voltage and memory effect depend on q/m(charge to mass ratio) of charged particle. In this case of breakdown voltage, the devices showed degradation of reflectivity and memory effect due to irregular movement of overcharged particles. In addition, contrast ratio of the device varies with memory effect. Thus, we consider that device needs uniform q/m for improvement of electric and optical properties and memory effect.

스마트 웨어러블용 NiTi계 선형 형상기억합금을 이용한 소프트 텍스타일 액추에이터 제작 및 동적 특성 측정 (Fabrication of Soft Textile Actuators Using NiTi Linear Shape Memory Alloy and Measurement of Dynamic Properties for a Smart Wearable)

  • 김상운;김상진;김주용
    • 한국의류학회지
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    • 제44권6호
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    • pp.1154-1162
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    • 2020
  • In this study, the soft textile actuator is produced for a smart wearable with the shape memory effects from linear shape memory alloys of Nickel and Titanium using the driving force through the fabrication process. The measurement model was designed to measure dynamic characteristics. The heating method, and memory shape of the linear shape memory alloy were set to measure the operating temperature. A shape memory alloy at 40.13℃, was used to heat the alloy with a power supply for the selective operation and rapid reaction speed. The required amount of current was obtained by calculating the amount of heat and (considering the prevention of overheating) set to 1.3 A. The fabrication process produced a soft textile actuator using a stitching technique for linear shape memory alloys at 0.5 mm intervals in the general fabric. The dynamic characteristics of linear shape memory alloys and actuators were measured and compared. For manufactured soft textile actuators, up to 0.8 N, twice the force of the single linear shape memory alloy, 0.38 N, and the response time was measured at 50 s.

Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

  • Kim, Hyun-Joo;Kim, Kyeong-Rok;Kwack, Kae-Dal
    • 한국신뢰성학회지:신뢰성응용연구
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    • 제10권1호
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    • pp.65-71
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    • 2010
  • NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

Event Recorder를 위한 Crash Protected Memory 개발 (Development of Crash Protected Memory for Event Recorder)

  • 송규연;이상남;류희문
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2010년도 춘계학술대회 논문집
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    • pp.1068-1074
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    • 2010
  • In high speed railway, event recorder is essential system for analyzing the cause of train accident. It stores train operation sent by train control system in safe memory unit. Crash protected memory, the safe memory unit for event recorder, keeps the stored contents from severe environment. For crash protected memory, we have designed the architecture of concrete enclosure and controller board. Proposed system provides large volume of memory capacity and fault tolerance architecture. For checking the characteristics of proposed crash protected memory specification, the simulation is executed. Simulation results shows the designed crash protected memory meets all requirements.

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Technology of the next generation low power memory system

  • Cho, Doosan
    • International Journal of Internet, Broadcasting and Communication
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    • 제10권4호
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    • pp.6-11
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    • 2018
  • As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

Resistive Switching Characteristics of Amorphous GeSe ReRAM without Metalic Filaments Conduction

  • 남기현
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.368.1-368.1
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    • 2014
  • We proposed amorphous GeSe-based ReRAM device of metal-insulator-metal (M-I-M) structure. The operation characteristics of memory device occured unipolar switching characteristics. By introducing the concepts of valance-alternation-pairs (VAPs) and chalcogen vacancies, the unipolar resistive switching operation had been explained. In addition, the current transport behavior were analyzed with space charge effect of VAPs, Schottky emission in metal/GeSe interface and P-F emission by GeSe bulk trap in mind. The GeSe ReRAM device of M-I-M structure indicated the stable memory switching characteristics. Furthermore, excellent stability, endurance and retention characteristics were also verified.

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지역성을 이용한 하이브리드 메모리 페이지 교체 정책 (Page Replacement Policy of DRAM&PCM Hybrid Memory Using Two Locality)

  • 정보성;이정훈
    • 대한임베디드공학회논문지
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    • 제12권3호
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    • pp.169-176
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    • 2017
  • To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.