• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제14권7호
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• pp.713-717
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• 2008

최근 플래시 메모리 용량이 증가함에 따라 대용량의 데이타를 빠르게 검색하기 위한 효율적인 인덱싱 방법의 필요성이 증가하였다. 플래시 메모리는 기존 저장매체와 다른 여러 가지 하드웨어적인 특성이 있다. 특히, 쓰기 연산과 소거 연산은 비용이 매우 크고, 덮어쓰기 연산이 불가능하다. 본 논문에서는 플래시 메모리에 저장되는 데이타에 대해여 발생하는 잦은 쓰기 연산을 감소시켜 다양한 연산을 효율적으로 처리하는 인덱스 구조를 제안한다. 본 논문에서는 성능 평가를 통해 제안하는 인덱싱 방법의 우수성을 보인다.

• 정보처리학회논문지A
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• 제12A권7호
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• pp.621-626
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• 2005

플래시 메모리는 비휘발성(non-volatility), 빠른 접근 속도, 저전력 소비, 그리고 간편한 휴대성 등의 장점을 가지므로 최근에 다양한 임베디드 시스템에서 많이 사용되고 있다. 그런데 플래시 메모리는 그 하드웨어 특성상 플래시 변환 계층(FTL: Flash Translation ayer)이라는 시스템 소프트웨어를 필요로 한다. 본 논문에서는 LSTAFF(Large Sate Transition Applied Fast Hash Translation Layer)라 명명된 대블록 플래시 메모리를 위한 새로운 FTL 알고리즘을 제안한다. LSTAFF는 운영체제가 다루는 데이터 섹터 크기 보다 큰 플래시 메모리의 페이지를 고려한 FTL 알고리즘이며, 기존 FTL 알고리즘과 제안될 LSTAFF를 구현하여 플래시 시뮬레이터를 이용하여 성능을 비교하였다.

• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• 대한임베디드공학회논문지
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• 제12권3호
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• pp.185-192
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• 2017

Due to the characteristics of low power, high durability and high density, NAND flash memory is being heavily used in various type of devices such as USB, SD card, smart phone and SSD. On the other hand, because of another characteristic of flash cell with the limited number of program/erase cycles, NAND flash memory has a short lifetime compared to other storage devices. To overcome the lifetime problem, many researches related to the wear leveling have been conducted. This paper presents a method called a TCB (Tracking Cold Blocks) using more reinforced constraint conditions when classifying cold blocks than previous works. TCB presented in this paper keeps a MCT (Migrated Cold block Table) to manage the enhanced classification process of cold blocks, with which unnecessary migrations of pages can be reduced much more. Through the experiments, we show that TCB reduces the overhead of wear leveling by about 30% and increases the lifetime up to about 60% compared to BET and BST.

• Journal of Information Processing Systems
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• 제11권1호
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• pp.39-56
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• 2015

Continuous multi-interval prediction (CMIP) is used to continuously predict the trend of a data stream based on various intervals simultaneously. The continuous integrated hierarchical temporal memory (CIHTM) network performs well in CMIP. However, it is not suitable for CMIP in real-time mode, especially when the number of prediction intervals is increased. In this paper, we propose a real-time integrated hierarchical temporal memory (RIHTM) network by introducing a new type of node, which is called a Zeta1FirstSpecializedQueueNode (ZFSQNode), for the real-time continuous multi-interval prediction (RCMIP) of data streams. The ZFSQNode is constructed by using a specialized circular queue (sQUEUE) together with the modules of original hierarchical temporal memory (HTM) nodes. By using a simple structure and the easy operation characteristics of the sQUEUE, entire prediction operations are integrated in the ZFSQNode. In particular, we employed only one ZFSQNode in each level of the RIHTM network during the prediction stage to generate different intervals of prediction results. The RIHTM network efficiently reduces the response time. Our performance evaluation showed that the RIHTM was satisfied to continuously predict the trend of data streams with multi-intervals in the real-time mode.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1426-1427
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• 2006

Chalcogenide based phase-change memory has a high capability and potential for the next generation nonvolatile memory device. Fast writing speed, low writing voltage, high sensing margin, low power consume and long cycle of read/write repeatability are also good advantages of nonvolatile phase-change memory. We have been investigated the new material for the phase-change memory. Its composition is consists of chalcogenide $Ge_{1}Se_{1}Te_2$ material. We made this new material to solve problems of conventional phase-change memory which has disadvantage of high power consume and high writing voltage. In the present work, we are manufactured $Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}$ and $Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}$ sandwich triple layer structure devices are manufactured to investigate its electrical properties. Through the present work, we are willing to ensure a potential of substitutional method to overcome a crystallization problem on PRAM device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.154-155
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• 2007

PRAM(Phase-Change RAM) is a promising memory that can solve the problem of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. So, we studied new constitution of $Ge_1Se_1Te_2$ chalcogenide material and presented the method of reducing the contact size between $Ge_1Se_1Te_2$ and electrode. A small-contact-area electrode is used primarily to supply current into and minimize heat loss from the chalcogenide. In this letter, we expect the method of reducing the contact size between $Ge_1Se_1Te_2$ and electrode to decrease writing current.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• 한국정보과학회논문지:시스템및이론
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• 제32권9호
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• pp.483-490
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• 2005

플래시 메모리는 비 휘발성(non-volatility), 빠른 접근 속도, 저전력 소비, 그리고 간편한 휴대성 등의 장점을 가지므로 최근에 많은 임베디드 시스템에서 많이 사용되고 있다 그런데 플래시 메모리는 그 하드웨어 특성상 플래시 변환 계층(FTL. flash translation layer)이라는 시스템 소프트웨어를 필요로 한다. 이 FTL의 주요 기능은 파일 시스템으로부터 내려오는 논리 주소를 플래시 메모리의 물리 주소로 변환하는 일이다. 본 논문에서는 STAFF(State Transition Applied Fast Flash Translation Layer)라 불리는 FTL 알고리즘을 제안한다. 기존의 FTL 알고리즘에 비하여 STAFF는 적은 메모리를 필요로 하면서 기존 일반 방법인 블록 사상 방법에 비하여 5배 정도 좋은 성능을 보인다. 본 논문에서는 기존 FTL 알고리즘과 STAFF의 성능 비교를 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.210-213
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• 2004

The phase transition between amorphous and crystalline states in chalcogenide semiconductor films can controlled by electric pulses or pulsed laser beam; hence some chalcogenide semiconductor films can be applied to electrically write/erase nonvolatile memory devices, where the low conductive amorphous state and the high conductive crystalline state are assigned to binary states. Memory switching in chalcogenides is mostly a thermal process, which involves phase transformation from amorphous to crystalline state. The nonvolatile memory cells are composed of a simple sandwich (metal/chalcogenide/metal). It was formed that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively.