• 한국전자파학회논문지
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• 제23권3호
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• pp.361-366
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• 2012

본 논문에서는 TSMC 0.18 ${\mu}m$ CMOS 공정을 사용하여 저전력, 5.2 GHz 대역 저잡음 증폭기를 설계하였다. 제안된 회로는 5.2 GHz 대역 저잡음 증폭기 설계를 위해, 공통 게이트 구조를 이용하여 입력 정합을 하였다. 입력 정합단에 캐패시터 크로스 커플링 방법을 사용하여 적은 양의 전류를 흘려 적당한 이득을 얻었다. 추가적인 전력 소비 없이 부족한 이득을 증가시키기 위하여 전류 재사용 방법을 이용하여 공통 게이트 증폭단 위에 공통 소스 구조를 추가하였다. 전류 재사용단의 인덕터의 크기를 줄이기 위하여 캐패시터를 병렬로 연결함으로써 실효 인덕턴스 값을 증가시켜 인덕터의 크기를 줄였다. 제안된 회로는 5.2 GHz 대역에서 17.4 dB의 이득과 2.7 dB의 잡음 지수 특성을 갖는다. 저잡음 증폭기는 1.8 V의 공급 전압에 대해 5.2 mW의 전력을 소비한다.

• 대한수학회논문집
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• 제18권4호
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• pp.677-685
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• 2003

Let M be the vector space of all real S-measurable functions defined on a measure space (X, S, $\mu$). In this paper, we investigate some topological structure of T on M. Indeed, (M, T) becomes a topological vector space. Moreover, if $\mu$, is ${\sigma}-finite$, we can define a complete invariant metric on M which is compatible with the topology T on M, and hence (M, T) becomes a F-space.

• Structural Engineering and Mechanics
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• 제7권4호
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• pp.401-412
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• 1999

The purpose of this paper is to show how the Evolutionary Structural Optimization (ESO) algorithm developed by Xie and Steven can be extended to optimal design problems of thin shells subjected to thermal loading. This extension simply incorporates an evolutionary iterative process of thermoelastic thin shell finite element analysis. During the evolution process, lowly stressed material is gradually eliminated from the structure. This paper presents a number of examples to demonstrate the capabilities of the ESO algorithm for solving topology optimization and thickness distribution problems of thermoelastic thin shells.

• 대한수학회논문집
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• 제13권3호
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• pp.545-560
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• 1998

Let ø and A be denoted by the structure tensor field of type (1,1) and by the shape operator of a real hypersurface in a complex space form $M_{n}$ (c), c $\neq$ 0 respectively. The main purpose of this paper is to prove that if a real hypersurface in $M_{n}$ (c) satisfies $R_{ξ}$ øA = $AøR_{ξ}$, then the structure vector field ξ is principal, where $R_{ξ}$ / is the Jacobi operator with respect to ξ.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.29-34
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• 2015

This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 GHz based on SiGe HBT technology. Firstly, a 123-GHz oscillator was developed based on Colpitts topology, which showed -5 dBm output power and phase noise of -107.34 dBc/Hz at 10 MHz. DC power dissipation was 25.6 mW. Secondly, a 135 GHz mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 dB at 1 GHz IF at fixed LO frequency of 134 GHz. DC power dissipation was 3 mW, which mostly comes from the buffer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.23-32
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• 2011

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.279-280
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• 2012

In this paper, as a part of studying the fast battery charger, designed the charging system by applying dual converter. This dual converter was applied to the charging system for reducing time by dividing high current which prevents the damage of parts from heating of components. In this paper continued the task by switching the topology of the dual converter for fast charging battery into SISO, PISO, and PIPO. The study to derive the optimized system topology by analyzing the efficiency of charging system.

• 한국수학교육학회지시리즈B:순수및응용수학
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• 제29권1호
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• pp.93-102
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• 2022

The impact of programming languages in the research sector has helped lot of researchers to broaden their view and extend their work without any limitation. More importantly, even the complex problems can be solved in no matter of time while converting them into a programming language. This convenience provides upper hand for the researchers as it places them in a comfort zone where they can work without much stress. With this context, we have converted the research problems in Topology into programming language with the help of Python. In this paper, we have developed a Python program to find the weaker form of closed sets namely alpha closed set, semi closed set, pre closed set, beta closed set and regular closed set.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제8권3호
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• pp.202-206
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• 2008

We introduce the concept of interval-valued minimal structure which is an extension of the interval-valued fuzzy topology. And we introduce and study the concepts of IVF m-continuous and several types of compactness on the interval-valued fuzzy m-spaces.

• 대한전자공학회논문지SD
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• 제44권6호
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• pp.50-59
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• 2007

[ $0.18-{\mu}m$ ] CMOS 공정에서 1.2-V 2차 Full-Feedforward 구조의 ${\Sigma}{\Delta}$ 모듈레이터를 설계하였다. Full-Feedforward 구조는 Op-Amp의 성능 요구치를 크게 경감시키기 때문에 저전압 저전력 ${\Sigma}{\Delta}$ 모듈레이터를 만들기에 적합한 구조로 세계적으로 많이 채택되고 있는 추세이다. 그리고, Top-Down 설계 기법을 적용하여 ${\Sigma}{\Delta}$ 모듈레이터를 설계하였는데, 이를 위하여 Op-Amp의 유한한 DC-Gain과 Bandwidth 등 여러 가지 비이상적 효과들을 모델링하여 전달함수를 유도하였다.