• Proceedings of the KIEE Conference
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• 2005.04a
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• pp.134-139
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• 2005

This paper presents a cost effective quasi-resonant soft-switching PWM high frequency inverter with minimum circuit components. This inverter can achieve wider soft commutation, simpler power circuit configuration, smaller volumetric size, lower cost and wider power regulation range, higher-efficiency as compared with single ended quasi-resonant ZVS-PFM inverter and active voltage clamped quasi-resonant ZVS-PWM inverter. The operation principle of the proposed inverter is described on the basis of the simulation and experimental results, together with its operating performances in steady state. The operating performances of this unique proposed high frequency inverter based on ZVS and ZCS arms-related soft commutation principle is evaluated and discussed as compared with the active voltage-clamped ZVS-PWM inverter and a conventional single-ended ZVS-PFM inverter. The practical effectiveness of a novel type quasi-resonant soft-switching PWM high frequency inverter using IGBT is actually proved for consumer induction heated appliances as rice cooker, hot water producer, steamer and super heated steamer. The extended bidirectional circuit topology of quasi-resonant PWM high frequency inverter with minimum circuit components is demonstrated, which operate as the direct frequency changer.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.53-57
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• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.7-11
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• 2014

In this paper, we designed resistive MMIC mixer using $0.5{\mu}m$ p-HEMT process. This Mixer is designed to have a similar performance in -4 ~ 4 dBm local oscillator signal power level and to maintain a constant conversion loss and linear performance due to the variation of local signal. In order to have such characteristics, we designed new feedback circuit topology by using FET, and minimized performance change for LO signal power level variation, also obtain MMIC mixer characteristics which is able to apply in wideband. In the design result, When the LO signal power is -4 ~ 4 dBm, there was 6 dB conversion loss and it came up with the excellent result that IIP3 got over 30 dBm in 0.5 ~ 2.6GHz frequency band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2045-2051
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• 2009

A 5-GHz band Low Noise Amplifier(LNA) using SOI MOSFET is designed. To improve the noise performance, depletion-type SOI MOSFET is adopted, and it is designed by the two-stage topology consisting of common-source and common-gate stages for low-voltage operation. The fabricated LNA achieved an S11 of less than -10dB, voltage gain of 21dB with a power consumption of 8.3mW at 5.5GHz, and a noise figure of 1.7dB indicated that the depletion-type LNA improved the noise figure by 0.3dB compared with conventional type. These results show the feasibility of a CMOS LNA employing depletion-type SOI MOSFET for low-noise application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.280-283
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• 2004

This paper discribes the design concept, fabrication process and measuring result of 2.5kV Gate Commutated Thyristor devices. Integrated gate commutated thyristors(IGCTs) is the new power semiconductor device used for high power inverter, converter, static var compensator(SVC) etc. Most of the ordinary GTOs(gate turn-off thyristors) are designed as non-punch-through(NPT) concept; i.e. the electric field is reduced to zero within the N-base region. In this paper, we propose transparent anode structure for fast turn-off characteristics. And also, to reach high breakdown voltage, we used 2-stage bevel structure. Bevel angle is very important for high power devices, such as thyristor structure devices. For cathode topology, we designed 430 cathode fingers. Each finger has designed $200{\mu}m$ width and $2600{\mu}m$ length. The breakdown voltage between cathode and anode contact of this fabricated GCT device is 2,715V.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.954-957
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• 2007

AODV 에서는 RREQ 메시지 전송을 통해 라우팅 경로를 설정한다. Ad-hoc 네트워크에서 노드가 자주 이동하거나 전송 지연 시간이 클 경우 RREQ 메시지 발생이 증가한다. 이러한 네트워크 변동에 따른 RREQ 메시지 발생 증가는 결과적으로 데이터 패킷 수신율을 저하시킬 뿐만 아니라, 노드의 에너지 소모율도 증가시킨다. 본 논문에서는 네트워크 토폴로지 변동 상황을 감지하여 AODV 에서의 RREQ 메시지 발생 빈도를 효과적으로 조절하는 알고리즘을 제안하였다. 제안된 알고리즘을 50개의 노드가 10m/s 이하의 속도로 무작위로 이동하는 Ad-hoc 네트워크에 적용한 결과, 기존 AODV 알고리즘에 비해 RREQ 메시지 발생 빈도가 25% 감소하였다. 뿐만 아니라 RREP 패킷과 RERR 패킷 역시 각각 26% 및 31%씩 감소하였다. 모든 종류의 메시지 발생 빈도 수가 감소함에 따라 데이터 패킷 수신율은 3% 증가했으며, 에너지 소모율 역시 13% 감소하였다.

• Journal of IKEEE
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• v.13 no.1
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• pp.41-48
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• 2009

This paper describes an implementation of the analog front end (AFE) incorporated with the image signal processing (ISP) unit in the SoC, dominating the performance of the CCD image sensor system. New schemes are exploited in the high-frequency sampling to reduce the sampling uncertainty apparently as the frequency increases, in the structure for the wide-range variable gain amplifier (VGA) capable of $0{\sim}36\;dB$ exponential gain control to meet the needed bandwidth and accuracy by adopting a new parasitic insensitive capacitor array. Moreover, the double cancellation of the black-level noise was efficiently achieved both in the analog and the digital domain. The proposed topology fabricated in a $0.35-{\mu}m$ CMOS process was proved in a full CCD camera system of 10-bit accuracy, dissipating 80 mA at 15 MHz with a 3.3 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.597-604
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• 2006

An ultrawideband(UWB) $3.1{\sim}5.15$ GHz low-noise amplifier employing a novel input matching circuit and feedback topology are presented. The proposed UWB amplifier is Implemented in $0.18{\mu}m$ RF CMOS technology. Measurements show a NF of $3.4{\sim}3.9$ dB, a power gain of $12.8{\sim}14$ dB, better than -9.4 of input matching and, an input IP3 of -1 dBm, while comsuming only 14.5 mW of power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.