• 전력전자학회논문지
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• 제8권2호
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• pp.107-115
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• 2003

PMSM은 높은 토크 특성과 우수한 전력 밀도, 논은 효율 때문에 산업용 빛 가정용 기기로 널리 사용되고 있다. PMSM의 우수한 제어 수행을 위해서는 회전자 위치의 정확한 정보가 필요하다. 그러나 위치 센서의 가격이 비싸고, 열악한 환경에서 신뢰도가 떨어지기 때문에 최근에는 센서리스 알고리즘에 대한 연구가 많이 진행되고 있다. 본 논문에서는 회전자 위치의 추정을 위해 쇄교 자속의 도함수를 이용한다. 수치적 미분을 행하지 않고 전압 방정식과 측정된 상전류를 이용한 수식적 미분을 통해 쇄교 자속을 구하는 a-$\beta$ 변환과 수식적 미분을 이용한 새로운 센서리스 알고리즘을 제안한다. 제안된 센서리스 속도 제어 알고리즘이 실험을 통해 증명된다.

• 한국소음진동공학회논문집
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• 제19권12호
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• pp.1281-1288
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• 2009

Variation of dynamic characteristics of a low pressure turbine blade with crack length is studied in this paper via both experiments and finite element model. Since most of the turbine blades used in domestic power plants are imported from abroad, it is necessary to understand their dynamic behavior in advance. When experimentally obtained natural frequencies and mode shapes are compared with those from FEM results, they are close to each other in their magnitude. Then, it is more feasible to use finite element model for analyzing the dynamic characteristics of a blade under various operation conditions (rotation speed, temperature, etc) as well as with a crack in the blade.

• 한국전자통신학회논문지
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• 제14권6호
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• pp.1145-1152
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• 2019

본 논문에서는 디지털 회로와 저소비전력 및 고속연산의 장점을 가진 아날로그 회로를 혼용하기 위하여, 저전력 전류모드 12비트 ADC(: Analog to Digital Converter)를 제안하였다. 제안하는 12비트 ADC는 4비트 ADC의 cascade 구조를 사용하여 소비전력을 줄일 수 있었으며, 변환 current mirror 회로를 사용해 칩면적을 줄일 수 있었다. 제안된 ADC는 매그나칩/SK하이닉스 350nm 공정으로 구현하였고, Cadence MMSIM을 사용하여 post-layout simulation를 진행하였다. 전원전압 3.3V에서 동작하고, 면적은 318㎛ x 514㎛를 차지하였다. 또한 제안하는 ADC는 평균 소비전력 3.4mW의 저소비전력으로 동작하는 가능성을 나타내었다.

• ETRI Journal
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• 제41권6호
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• 전자공학회논문지D
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• 제35D권1호
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• pp.41-48
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• 1998

This paper proposes a new addition algorithm to improve the addition speed which is one of the important factors for data path functions. We have designed a fast 64-bit adder utilizing al dynamic chain architecture based on the proposed Sum-Selector Generation (SSG) algorithm. Proposed adder is designed with pass-transistor logicto achieve a high speed operation in low voltage circumstance. Realized 64-bit adder with 0.8.mu.m CMOS double-metal process technology has been fully tested. it operates at 185 MHz with 5.0V and chip area occupies 3.66mm$^{2}$. It is also demonstrated that designed adder operates even at 2.0V power supply condition.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.443-446
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• 2002

Brushless DC motor(BLDCM) are suitable to operate in a wide speed range, easy to control and since there are no mechanical brushes and commutators, require low maintenance costs and are free from restrictions of application environment. And since the ratio of instantaneous torque and rated torque is high, BLDCM are appropriate for variable speed operation. This paper proposes the optimal model by using Matlab/simulink based on modelling and characteristic analysis of trapezoidal back EMF type BLDCM and verifies the validity of the proposed model by applying control systems.

• Progress in Superconductivity
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• 제9권2호
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2006년도 추계학술대회 논문집
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• pp.1214-1221
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• 2006

In this paper, development and performance characteristic of propulsion system(Converter/Inverter) using IPM(Intelligent Power Module) for 120km/h AC electric vehicle is proposed. The proposed propulsion system is comprised of IPM converter and inverter stack which uses natural air-cooling system, DC-Link, OVCRf unit and control unit. And also 2-Parallel operation of two PWM converter is adopted for increasing capacity of system and the VVVF inverter control is used a mixed control algorithm, where the vector control strategy at low speed region and slip-frequency control strategy at high speed region. The proposed propulsion system is verified by main line test results as well as combined test results.

• 정보저장시스템학회논문집
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• 제7권1호
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• pp.7-12
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• 2011

The flash memory has been remarked as the next generation media of portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major data storage components for desktop and servers. The purpose of our study is to upgrade a traditional mirroring scheme based on SSD storages due to the relatively slow or freezing characteristics of write operations, as compared to fast read operations. For this work, we propose a new storage management scheme called Memory Mirror-Switching based on traditional mirroring scheme. Our Mirror-Switching scheme improves flash operation performance by switching write-workloads from flash memory to RAM and delaying write operations to avoid freezing. Our test results show that our scheme significantly reduces the write operation delay and storage freezing.

• 한국인터넷방송통신학회논문지
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• 제9권1호
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• pp.39-45
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• 2009

본 논문에서는 최근 무선 통신 시스템에서 빠른 데이터전송 방식으로서 사용되고 있는 OFDM 통신방식의 저소비전력화 방안을 제안한다. 일반적으로 OFDM에서 주요 신호처리 방식은 디지털을 이용한 프리에 변환이다. 이런 디지털 프리에 변환은 많은 소비전력이 필요하며 이것은 무선통신 시스템에 있어서 커다란 제약이 되고 있다. 전류모드를 이용한 아날로그 프리에 변환(FFT) LSI는 이러한 소비전력의 문제를 해결할 수 있는 주요 대안으로 떠오르고 있다. 그러나 이러한 신호처리 방식을 사용하기 위해서는 전류모드를 이용한 직병렬/병직렬 변환기(Serial-to-Parallel/Parallel-to-Serial Converter)가 필수적으로 필요하다. 본 논문에서는 전류모드로 구성한 아날로그 프리에 변환(FFT) LSI를 이용해 수신단의 저소비전력을 실현하기 위해 필수적인 새로운 전류모드 직병렬/병직렬 변환기를 제시하였으며 설계된 칩의 측정결과가 시뮬레이션 결과와 일치하는 것을 확인하였다. 제안된 전류모드 직병렬/병직렬 변환기의 개발로 저소비전력에 큰 장점을 지니고 있는 아날로그 FFT LSI의 활용이 가능해졌으며 송수신단 시스템에서 큰 소비전력의 감소효과를 가져올 것으로 기대된다.