• The Journal of the Acoustical Society of Korea
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• v.30 no.4
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• pp.190-196
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• 2011

Bandwidth extension is a technique to improve speech quality and intelligibility, extending from 300-3400 Hz narrowband speech to 50-7000 Hz wideband speech. This paper designs an artificial bandwidth extension (ABE) module embedded in the AMR (adaptive multi-rate) decoder, reducing LPC/LSP analysis and algorithm delay of the ABE module. We also introduce a fast search codebook mapping method for ABE, and design a low power BWE technique based on the AMR decoder. The proposed ABE method reduces the computational complexity and the algorithm delay, respectively, by 28 % and 20 msec, compared to the traditional DTE (decode then extend) method. We also introduce a weighted classified codebook mapping method for constructing the spectral envelope of the wideband speech signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2121-2130
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• 2015

In this paper, we analyze LM-MIMO (load-modulation multiple-input multiple-output) system with single RF chain. And then, we confirm that load modulation technique can support generation of high-order m-PSK modulation and m-QAM modulation in LM-MIMO system. Finally we evaluate performance of LM-MIMO system with load modulation. Conventional MIMO system requires a number of RF chains for expansion of MIMO dimension. A number of RF chains can cause various problems. On the other hand, although LM-MIMO system is expanded, LM-MIMO system requires single RF chain only. Therefore, LM-MIMO system has low-complexity and low power consumption. As results, we can confirm that load modulation of T-model can modulate high-order m-PSK and m-QAM singal. Also, we can confirm that $4{\times}4$ LM-MIMO system using load modulation has a similar performance to conventional $4{\times}4$ MIMO system.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1287-1296
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• 2007

Recently, the high speed railway comes into the spotlight as the important and convenient traffic infrastructure. In Korea, Kyung-Bu high speed train service began in about 400km section at 2004, and the Ho-Nam high speed railway will be constructed by 2017. The high speed train will run with a design maximum speed of 300-350km/hr. Since the trains are operated at high speed, the differential settlement of subgrade under the rail is able to cause a fatal disaster. Therefore, the differential settlement of the embankment must be controlled with the greatest care. Furthermore, the characteristics and causes of settlements which occurred under construction and post-construction should be investigated. A considerable number of studies have been conducted on the settlement of the natural ground over the past several decades. But little attention has been given to the compression settlement of the embankment. The long-term settlement of compacted fills embankments is greatly influenced by the post-construction wetting. This is called 'hydro collapse' or 'wetting collapse'. In spite of little study for this wetting collapse problem, it has been recognized that the compressibility of compacted sands, gravels and rockfills exhibit low compressibility at low pressures, but there can be significant compression at high pressures due to grain crushing by several researchers(Marachi et al. 1969, Nobari and Duncan 1972, Noorany et al. 1994, Houston et al. 1993, Wu 2004). The characteristics of compression of fill materials depend on a number of factors such as soil/rock type, as-compacted moisture, density, stress level and wetting condition. Because of the complexity of these factors, it is not easy to predict quantitatively the amount of compression without extensive tests. Therefore, in this research I carried out the wetting collapse tests, with focusing in various soil/rock type, stress levels, wetting condition more closely.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.6
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• pp.1-9
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• 2010

In this paper, we propose a hi-speed/low-power Extended QRD-RLS(QR-Decomposition Recursive Least Squares) equalizer with systolic array structure. In the conventional systolic array structure, vector mode CORDIC on the boundary cell calculates angle of input vector, and the rotation mode CORDIC on the internal cell rotates vector. But, in the proposed structure, it is shown that implementation complexity can be reduced using the rotation direction of vector mode CORDIC and rotation mode CORDIC. Furthermore, calculation time can be reduced by 1/2 since vector mode and rotation mode CORDIC operate at the same time. Through HDL coding and chip implementation, it is shown that implementation area is reduced by 23.8% compared with one of conventional structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8A
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• pp.618-624
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• 2009

In the evolution from wireless sensor networks(WSNs) to ubiquitous sensor networks(USNs), technologies that can support intensive data-traffic loads, large number of users, improved interoperability, and extreme longevity are required. Therefore, efficient communication time coordination control and low power consumption becomes one of the most important design goals for USN MAC protocols. So far several time division multiplexed (TDM) MAC protocols have been proposed. However, since the pros and cons of existing protocols are not easy to analyze, it becomes a challenging task to design improved TOM MAC protocols. Based on this objective, this paper provides a novel protocol analysis along with a message complexity derivation and comparison of the existing TDM MAC protocols.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.47-52
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• 2009

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.

• Korean Journal of Human Ecology
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• v.13 no.2
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• pp.271-282
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• 2004

The purposes of this study were to research the behavior of consumption and needs about the female university students to provide useful information which would help finding the marketing source of cosmeceuticals. The sample was consisted of 464 female university students who had experiences of using the cosmeceuticals. Data were analyzed by factor analysis, frequency, x2-test, t-test, ANOVA(LSD) using SPSSWIN. The results were as follows: When the female university students purchased the cosmeceuticals, they considered the effectiveness and the price, so were satisfied with good effect and low price. The most important marketing methods in cosmeceuticals for female university students were through the internet and mail order shopping. Whereas, demerit factors of internet shopping were founded to be the complexity of exchange or refund and the little chance of free samples for trial. The good marketing strategies might be sending trial samples, future payment system after trial period, and/or supporting the event held in the university. Besides, it might be a consideration to have an event for the improvement by public trial. Anti-aging cosmeceutical was the most preferred item for female students, sun protection and whitening cosmetics next in order. Therefore, a target customer for cosmeceuticals might be lowered in age. The purchasing cost system and therapeutic effect of cosmeceuticals had to be developed for 20's. It was necessary to be safe and effective. The factors affecting the level of satisfaction for cosmeceuticals could be categorized into 4; market environment, simplicity of purchase, product merit and additional service. The needs for cosmeceuticals showed significant differences according to grade and kinds of product.