• Fashion & Textile Research Journal
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• v.1 no.1
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• pp.69-73
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• 1999

Korean and Japanese, both people have a lot of similarity and complexity in terms of physical constitution and culture. This study might be the first implementation that tries to figure out constitutional differences of both people in scientific way. In this study, subjects were from each country, had been exposed $5^{\circ}C$ environment wearing each country's traditional costume- so called Hanbok and Kimono- and all through this experiment we'd compared physiological responses and analyzed differences of cold response go with their own clothing culture. We've obtained following results: Korean had kept maintaining low mean skin temperature basically in cold circumstance, compared with Japanese, have stronger cold tolerance. However, there's no significant difference between Korean and Japanese. Owing to huge influence of wearing other country's traditional costume itself even makes differences of rectal temperature in a cold environment. In addition, in a period of time that wearing other country's traditional costume, thermal sensation would be different according to exposed surrounding temperature.

• Proceedings of the Korean Institute of Interior Design Conference
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• 2008.05a
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• pp.280-284
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• 2008

This study is a research for revitalized characteristics of compounded community center which is a complex aid facility with a key position of regional culture and welfare. Recent complex conditions of community center and public facility is studied on this research. The methods are searches in the Internet, telephone interviews, and documents of present local conditions. The results are as follow : The community center in Seoul City support 2 million people per a center in average and self-supporting financial rate came out low. The community center formed physical shape in one building with community facilities. A district complex community center type, which is a village office united to public facilities, expected to be increased. The community center compound 1 or 2 facilities, divided 15 types. Most of community center is complex type of community center with village office and the other types are complex type of community center with a hall for the aged, nursery, and library. Accordingly, the community center keeps up the complex type of community center with village office type as a physical shape in one building and the district complex community center type complexes with hall for the aged, nursery and library.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.550-559
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• 2005

The matrix converter provides sinusoidal input and output wave forms, bidirectional power flow, controllable input power factor and a long life, compared to the VSI(Voltage Source Inverter) with diode rectification stage at the input. However it has tasks, such as complexity of the control method, ride-through problem and low voltage-ratio limitation, to overcome for commercializing, This paper describes the design, construction and implementation of matrix converter based on space vector modulation technique. The implemented prototype of matrix converter is built using the exclusive IGBT module and control circuit constituted with DSP and CPLD and it has an input filter, overvoltage protection circuit and commutation means for overcoming practical issues. The good results tested using an induction motor are also presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• Archives of design research
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• v.19 no.2 s.64
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• pp.121-128
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• 2006

The elements to enhance preference in symbol design are mainly related to consumers' response and aesthetic elements. Because certain aesthetic elements in design affect consumers' response and it is actually presented through (the different level of) preference. This study through surveying case studies examines whether a certain aesthetic element in symbol design gives rise to much preference. According to the result of study, high preference in symbolic design depends on high level of Rhythm, Balance, Harmony, Elaboration, Round, Gestalt, Organic, and Artificial/Natural among aesthetic elements. In comparison, it is founded that Simplicity/complexity, Objective/Abstract, depth, and symmetry should be designed at the moderate level, and proportion, repetition of elements be at the low level. Additionally(or Besides) this study makes out that symbol design cases with high preference have shapes from natural material or patterns of traditional culture, while cases with low preference have shapes from geometric figures. On the basis of these results, a guideline of symbol design could De offered(or suggested) to fit preference of consumers. But, this study is mostly concerned with only affect among emotional reactions of consumer in a scope of study, and is considered only in the aspect of form excluding color and texture.

• Journal of the Korean Data and Information Science Society
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• v.21 no.2
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• pp.211-218
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• 2010

Taguchi has used the signal-to-noise ratio (SN) to achieve the appropriate set of operating conditions where variability around target is low in the Taguchi parameter design. Many Statisticians criticize the Taguchi techniques of analysis, particularly those based on the SN. Moreover, there are difficulties in practical application, such as complexity and nonlinear relationships among quality characteristics and design (control) factors, and interactions occurred among control factors. Neural networks have a learning capability and model free characteristics. There characteristics support neural networks as a competitive tool in processing multivariable input-output implementation. In this paper we propose a substantially simpler optimization procedure for parameter design using neural network without resorting to SN. An example is illustrated to compare the difference between the Taguchi method and neural network method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• Journal of KIISE:Software and Applications
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• v.31 no.8
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• pp.980-990
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• 2004

The component-based development methodology aims at the high state of abstraction and the reusability with components larger than classes. It is indispensible to measure the component so as to improve the quality of the component-based system and the individual component. And, the quality of the component should be improved through putting the results into the process of the development. So, it is necessary to study the component metric which can be applied in the stage of the component analysis and design. Hence, in this paper, we propose component cohesion, coupling, independence metrics reflecting the information extracted in the step of component analysis and design. The proposed component metric bases on the similarity information about behavior patterns of operations to offer the component's service. Also, we propose the redesigning process for the improvement of component design. That process uses the techniques of clustering and is for the thing that makes the component as the independent functional unit having the low complexity and easy maintenance. And, we examine that the component design model can be improved by the component metrics and the component redesigning process.