• Korean Journal of Human Ecology
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• v.14 no.4
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• pp.683-692
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• 2005

This study was intended to analyze the clothing shopping orientations and purchasing practices for men's dress shirts. It was conducted by means of convenience sampling survey with male office workers who usually wear dress shirts at work and who also live in Seoul, Geonggi, and Chungcheong area. The data collected were analyzed by frequency analysis, cross-tabulation analysis, factor analysis, t-test, and ANOVA using SPSS. The results are as follows: 1) Clothing shopping orientations were classified into six factors: brand oriented; planned; enjoying; expediency oriented; negative shopping; and low price oriented. There were partially significant differences in clothing shopping orientations according to the surveyees' age. 2) The surveyees prioritized low price and expediency in clothing shopping, but they also showed low interest in brands. 3) The criteria for purchasing were in the order of size, color, comfort, and design. There were also partially significant differences in the estimation criteria for dress shirts according to marital status and age. 4) Most respondents tended to purchase 3 or 4 pieces of dress shirts a year, paying 30,000 to 50,000 won for a piece, usually at department stores. 5) When they purchase a dress shirt, they always considers its size. In the case of married men, however, it is the laundry tag that they do care about.

• Journal of the Korean Society of Costume
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• v.65 no.8
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• pp.22-34
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• 2015

This study was intended to investigate the influences of consumer's self-monitoring, pioneer brand awareness, types of endorsers on quality perception of "me-too" brands with a focus on outdoor brands. The design of this research was comprised of 2 types of self-monitoring(high vs. low), 2 types of pioneer brand awareness(high vs. low), 2 types of endorsers(professional expert vs. typical consumer). The study was carried out by using samples from residents of Seoul and Gyeonggi area. The number of subjects used in the final analysis totaled 243, with age of the consumers ranging grom 20's to 50's. The results of this study were as follows. Self-monitoring, pioneer brand awareness and types of endorsers had shown a statistically significant correlation effect on the quality perception of me-too brands. Especially, in the high-level self-monitoring group, the effect of pioneer brand awareness on quality perception of me-too brand was significant when typical consumer model was given. The result presents that using a professional expert model in the market rather than a typical consumer model can offset the quality perception of pioneer brand with low awareness.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• Proceedings of the Korea Concrete Institute Conference
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• 2006.05a
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• pp.218-221
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• 2006

The past Korean Bridge Design Specifications have no limitation on the amount of lap splices of longitudinal bars in the plastic hinge zone of piers. A majority of bridge piers which have been non-seismically designed might have some lap splices in plastic hinge zone. Also a number of those piers in Korea have a low aspect ratio(height/section area). So, some problems such as low ductility behavior may happen. In this study, the real pier which was non-seismically designed and has a low aspect ratio was selected for the quasi-static tests. Two groups of full scaled RC pier models of which aspect ratios are about 2.26 and about 2.67 were fabricated. And then, quasi-static tests according to the drift level history method were implemented. From the test results, the failure of these test specimens have been shown in the complex shear-flexural or shear modes. The low aspect ratio and the lap splice have largely influenced on the seismic performance of bridge piers.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.35-39
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• 2000

Large-area high-temperature superconducting (HTS) films, filter design and damage-free processing technique have been developed to fabricate low insertion loss and sharp skirt filters. Further, long life cryocooler, low temperature low noise amplifier (LNA) and cryocable have been developed to assemble HTS filter subsystem for IS-95 and IMT-2000 mobile telecommunication. The surface resistance of the films was about 0.2 milli-ohm at 70 K, 12 GHz. An 11-pole HTS filter for IS-95 telecommunication system and a 16-pole HTS filter for IMT-2000 telecommunication system were designed and fabricated using 60 {\times}$ 50 mm$^2$ and one half of 3-inch diameter YBCO films on a 0.5-mm-thick MgO substrate, respectively. We have assembled the filter and low temperature LNA in a dewar with the cryocooler. Ultra low-noise (noise figure: 0.5 dB at 70 K) and ultra sharp-skirt (40 dB/1.5 MHz) performance was presented by the IS-95 filter subsystem and the IMT-2000 filter subsystem, respectively.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.133-134
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• 2006

In this paper the platform system for IEEE 802.15.4 Low Rate WPAN is designed and fabricated. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home-area network. According to the IEEE 802.15.4 standard, there are two modes, One is BPSK modulation in 868/915MHz frequency band. The other is O-QPSK modulation in 2.45GHz frequency band. In this paper we implemented the platform system mounted in one PCB board in 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. We measured that the platform system which consists of digital part and RF part has good performance. Also RF part is realized by design and fabrication of the RF transceiver IC. The key issue is to make the platform system which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.671-678
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• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.2
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• pp.79-87
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• 2011

This paper presents the optimal design of an overlapped ultrasonic sensor ring for high resolution obstacle detection of an autonomous mobile robot. It is assumed that a set of low directivity ultrasonic sensors of the same type are arranged along a circle of nonzero radius at a regular spacing with their beams overlapped. First, taking into account the dead angle region, the entire range of obstacle detection is determined with reference to the center of an overlapped ultrasonic sensor ring. Second, the optimal design index of an overlapped ultrasonic sensor ring is defined as the area closeness of three sensing subzones resulting from beam overlap. Third, the lower and upper bounds on the number of ultrasonic sensors are derived, which can guarantee minimal beam overlap and also avoid excessive beam overlap among adjacent ultrasonic sensors. Fourth, employing a commercial low directivity ultrasonic sensor, an optimal design example of an overlapped ultrasonic sensor ring is given along with the ultrasonic sensor ring prototype mounted on top of a mobile robot. Finally, some experimental results using our prototype ultrasonic sensor ring are given to demonstrate the validity and performance of an optimally overlapped ultrasonic sensor ring for high resolution obstacle detection.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.1
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• pp.31-38
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• 2019

In this paper, we develop a beamforming front end platform with pipeline circuit configuration method that can apply various clinical diagnostic applications of ultrasound image technology. Hardware design targets compression applications as well as scalable applications where power, integration levels and replication possibilities are important. Firmware design was implemented to achieve optimal FPGA parallel processing level by constructing new IP and system-oriented design environment to accelerate design productivity with maximum productivity improvement using Vivado HLS tool, which is a next generation high level synthesis tool. Former supports the high-speed management function of scan data that can create an image area arbitrarily and can be appropriately corrected and supplemented when reconfiguring or changing system specifications in the future.