Journal of Korea Society of Industrial Information Systems (한국산업정보학회논문지)

Korea Society of Industrial Information Systems (한국산업정보학회)
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FPGA-Based Low-Power and Low-Cost Portable Beamformer Design

FPGA 기반 저전력 및 저비용 휴대용 빔포머 설계

  • Received : 2018.10.30
  • Accepted : 2019.02.08
  • Published : 2019.02.28
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Abstract

In this paper, we develop a beamforming front end platform with pipeline circuit configuration method that can apply various clinical diagnostic applications of ultrasound image technology. Hardware design targets compression applications as well as scalable applications where power, integration levels and replication possibilities are important. Firmware design was implemented to achieve optimal FPGA parallel processing level by constructing new IP and system-oriented design environment to accelerate design productivity with maximum productivity improvement using Vivado HLS tool, which is a next generation high level synthesis tool. Former supports the high-speed management function of scan data that can create an image area arbitrarily and can be appropriately corrected and supplemented when reconfiguring or changing system specifications in the future.

본 논문에서는 초음파 응용 영상 기술의 다양한 임상 진단 응용이 가능한 파이프라인 회로 구성 방식을 가지는 빔포밍 프런트 엔드 플랫폼을 개발한다. 하드웨어 설계에서는 전력, 통합수준 및 복제 가능성이 중요한 확장 가능한 애플리케이션은 물론 압축 애플리케이션을 대상으로 한다. 펌웨어 디자인으로는 차세대 고수준의 합성 도구인 Vivado HLS 툴을 사용하여 최대의 생산성 향상으로 설계 생산성을 가속화하는 새로운 IP 및 시스템 중심 설계 환경 구축을 통하여 최적의 FPGA 병렬 처리 수준을 달성 하도록 구현하였다. 설계된 디지털 빔포머는 향후 시스템 사양의 재구성이나 변경시 적절한 수정 및 보완이 가능하고, 임의의 이미지 영역을 생성할 수 있는 스캔 데이터의 고속 관리 기능을 지원한다.

Keywords

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Fig. 2 Full Beamformer System and Related Components.

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Fig. 4 Internal Structure of US Beamformer Receiver

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Fig. 5 Test Bench for Digital Beam Former Start Scan Clock Signal Generation

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Fig. 6 Added scanData by webs(Write Enable Bar for startScan) signal

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Fig. 7 Result of Loading Register Value of Scan Data by Webs Signal

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Fig. 1

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Fig. 3

Table 1 Characteristics of the DesignedBeamformer Reported by Vivado

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References

  1. Lee, Y. J., and Lee, H. H., "Ultrasonic Application and Recent Trends in Diagnostic Medical Imaging," The Magazine of the IEIE, Vol. 44, No. 3, pp. 40-50, 2017.
  2. Ma, J., Karadayi, K., Ali, M., and Kim, Y., "Software-based Ultrasound Phase Rotation Beamforming on Multi-core DSP," in Proc. IEEE International Ultrasonics Symposium, pp. 503-506, 2011.
  3. Basem Ahmed Hassan, "Low-Cost Digital Ultrasound Beamformer Design using Field Programmable Gate Arrays," Master's Thesis, Cairo University, 2012.
  4. Chen, K., Lam, B., Sodini, C. G., and Chandrakasan, A. P., "System Energy Model for a Digital Ultrasound Beamformer with Image Quality Control," in Proc. IEEE International Ultrasonics Symposium, pp. 615-618, 2012.
  5. Park, H. N., and Lee, J. G., "Ultrasonic Beamforming Design and CUDA Performance Comparison using OpenCL," in Proc. The Institute of Electronics and Information Engineers 2014 Summer Symposium, Vol. 37, No. 1, pp. 1103-1106, 2014.
  6. Lim, B. G. and Kang, M. H., "HW/SW Co-design For an Ultrasonic Signal Processing System Using Zynq SoC," Journal of The Institute of Electronics and Information Engineers, Vol. 51, No. 8, pp. 148-155, 2014. https://doi.org/10.5573/ieie.2014.51.8.148
  7. Xilinx, Vivado Design Suite User Guide, Programming and Debugging, UG908, Apr 20, 2017.
  8. Spaulding, J., Eldar, Y. C,. and Murmann, B., "A Sub-Nyquist Analog Front-End with Subarray Beamforming for Ultrasound Imaging," in Proc. IEEE International Ultrasonics Symposium, 2015.
  9. Xilinx 7 Series FPGAs Data Sheet: Overview, DS180, Mar. 28, 2017.