• 대한전자공학회논문지SD
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• 제44권12호
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• pp.93-101
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• 2007

작은 면적과 저전력으로의 구현은 다양한 멀티미디어 하드웨어, 특히 모바일 환경에서 매우 중요한 요구사항이다. 본 논문은 작은 면적과 그에 따른 저전력을 목표로 H.264/AVC 인트라 예측기기 하드웨어 구조를 제안한다. 이미지 프레임을 예측하기 위해 하나의 연산기로 모든 모드 결정과 계산들이 순차적으로 수행기고 그들 중 최적의 값을 선택하는 방식이며, 그 결과로 다른 기존의 논문들 보다 더 작은 면적의 결과를 얻을 수 있었다. 제안된 구조는 Altera Excalibur device를 이용하여 검증되었고, 구현된 하드웨어 구조는 Synopsys Design Compiler와 Samsung STD130 0.18um CMOS Standard Cell Library를 이용하여 합성하였다. 합성결과 크기는 11.9k의 하드웨어 로직 게이트와 1078 byte의 내부 SRAM을 사용하고 최대 동작 주파수는 약 107MHz가 되었다. 제안한 구조는 하나의 QCIF($176\times144$ 화소) 영상 프레임을 처리하는데 879,617클록이 소요되며, 이는 QCIF 영상을 초당 121.5프레임으로 처리가 가능하며, 이는 하드웨어 기반의 실시간 H.264/AVC 부호화 시스템에 적합한 구조임을 보여준다.

• Geomechanics and Engineering
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• 제20권2호
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• pp.131-146
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• 2020

Evaluation of earthquake impacts in settlements with a high risk of earthquake occurrence is important for the determination of site-specific dynamic soil parameters and earthquake-resistant structural planning. In this study, dynamic soil properties of Karliova (Bingol) city center, located near to the intersection point of the North Anatolian Fault Zone and the East Anatolian Fault Zone and therefore having a high earthquake risk, were investigated by one-dimensional equivalent linear site response analysis. From ground response analyses, peak ground acceleration, predominant site period, 0.2-sec and 1-sec spectral accelerations and soil amplification maps of the study area were obtained for both near-field and far-field earthquake effects. The average acceleration spectrum obtained from analysis, for a near-field earthquake scenario, was found to exceed the design spectra of the Turkish Earthquake Code and Eurocode 8. Yet, the average acceleration spectrum was found to remain below the respective design spectra of the two codes for the far-field earthquake scenario. According to both near- and far-field earthquake scenarios in the study area, the low-rise buildings with low modal vibration durations are expected to be exposed to high spectral acceleration values and high-rise buildings with high modal vibration durations will be exposed to lower spectral accelerations. While high amplification ratios are observed in the north of the study area for the near-distance earthquake scenario, high amplification ratios are observed in the south of the study area for the long-distance earthquake scenario.

• 한국비블리아학회지
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• 제22권2호
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• pp.201-220
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• 2011

도서관은 모든 이용자의 정보접근권을 보장해야 하는 사회적 기관이다. 이러한 관점에서 본 연구에서는 도서관 웹사이트를 통한 평등한 정보접근에 대해 이론적 근거를 제공하기 위해 유니버설 디자인의 개념을 분석하고, 이를 바탕으로 도서관 웹사이트 평가기준을 개발하였다. 그리고 이 평가기준을 이용하여 7개의 지역대표도서관 웹사이트를 평가한 각 웹사이트의 유니버설 디자인 준수율을 측정하였다. 평가 결과, 대부분의 웹사이트가 웹 접근성과 사용성 영역에서는 높은 준수율을 보였으나, 유니버설 디자인의 본질적 속성인 평등한 이용이나 이용의 유연성 측면에서는 준수율이 매우 낮은 것으로 나타났다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2004년도 추계학술대회 논문집
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• pp.652-656
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• 2004

Crashworthy design of trains is now indispensable procedure in modern railway vehicle design for ensuring the safety of Passengers and crew. It is now widely recognized that a more strategic approach is needed in order to absorb higher level energy in a controlled manner and minimize passenger injuries effectively. The first design step in this strategic approach is the design of the front end structure(so called HE extremities) to absorb a large part of total impact energy and then the structure of passengers non-accommodation zones(so called LE extremities) is designed to absorb the rest of impact energy. In this paper, the passengers entrance door area is selected as the LE(low energy) extremities and the design of the LEE was carried out. The main part of LEE design procedures is the design of energy absorbing tubes. For this purpose, the several tube candidates are introduced and compared to each others with numerical crash simulation.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 1999년도 춘계 학술대회논문집
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• pp.177-185
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• 1999

The airfoil design optimization procedures based on the Navier-Stokes equations were developed, This procedure enables more realistic and practical transonic airfoil designs. The modified Hicks-Henne functions were used to generate the shape of airfoils. Five Hick-Henne functions were used to design upper surface of airfoil only. To enhance the ability of Hick-Henne function to generate various airfoil shape with limited number of functions, the positions of control points were adjusted through optimization procedure. The design procedure was applied to the single-point design for the drag minimization problem with lift and area constraints. The result shows the capability of the procedure to generate much realistic airfoils with very small drag-creep in the low transonic regime. This is mainly due to the viscosity effect of Navier-Stokes flow analysis. However, in the higher transonic range tile drag-creep appears. The multi-point design is shown to be an effective way to avoid the drag-creep and improve off-design performance which is very similar in the Euler design.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.459-462
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• 2004

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 1999년도 제12회 학술강연회논문집
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• pp.24-24
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• 1999

This study addresses the effectiveness of TEC(Thermoelectric cooler) application for spacecraft thermal control. The required radiator area and power consumption characteristics of active thermal control using TEC are compared with the passive control at BOL and EOL through unsteady thermal analyses by calculating external heat fluxes. When the component operating temperature is low enough in TEC active control, the required radiator area can be smaller than the passive thermal control. TEC also needs less power consumption than the passive control under the condition that the temperature of cooling pars is low enough and/or the design temperature margin of the components is narrow enough.

• ETRI Journal
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• 제43권6호
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• pp.1113-1129
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• 2021

Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

• 대한전자공학회논문지SD
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• 제37권10호
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• pp.73-81
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• 2000

본 논문은 분할된 look up table(LUT) 구조를 갖는 전력 소모 및 면적에 효율적인 보간 저역통과 여파기의 설계에 관한 것이다. 제안한 보간 여파기는 계수 대칭성과 LUT 데이터들이 대칭성을 이용하여 면적이 최소화된다. 최소의 면적으로 위상에 따라 분할된 LUT는 두개의 여파기가 공유하고 선택적으로 활성화됨으로써 저 전력 동작을 수행한다. 제안된 여파기는 5.0V 0.6${\mu}m$ CMOS 공정으로 설계되었으며 전력 소모 시뮬레이션은 Powermill을 사용하여 수행하였다. 기존에 제안된 여파기들과의 비교 실험 결과를 통하여 제안한 필터의 전력 소모는 26% 감소하였고 게이트 면적은 5% 감소하였음을 보인다.