• 제목/요약/키워드: low-area design

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Digital Front-End Design에서의 반도체 특성 연구 및 방법론의 고찰 (Semiconductor Characteristics and Design Methodology in Digital Front-End Design)

  • 정태경;이장호
    • 한국정보통신학회논문지
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    • 제10권10호
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    • pp.1804-1809
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    • 2006
  • 본 고에서는 디지털 회로의 저 전력소모의 설계와 구현에 관련된 디지털 전대역 회로 설계를 통해서 전반적인 전력 소모의 방법론과 이의 특성을 고찰하고자 한다. 디지털 집적회로의 설계는 광대하고 복잡한 영역이기에 우리는 이를 저전력 소모의 전반적인 회로 설계에 한정할 필요가 있다. 여기에는 로직회로의 합성과, 디지털 전대역 회로설계에 포함되어 있는 입력 clock 버퍼, 레치, 전압 Regulator, 그리고 케페시턴스와 전압기가 0.12 마이크론의 기술로 0.9V의 전압과 함께 쓰여져서 동적 그리고 정적 에너지 소모와 압력, 가속, Junction temperature 등을 모니터 할 수 있게 되어 있다.

RFID의 경량화된 암호 알고리즘의 하드웨어적 설계의 문제점 분석 (Hardware Design Issues of Light-weight Crypto Algorithms for RFID)

  • 김정태
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 춘계학술대회
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    • pp.643-645
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    • 2011
  • We analysed a hardware design issues, which is strong, compact and efficient. Due to its low area constraints, primitive based on hardware is especially suited for RFID (Radio Frequency Identification) devices. primitive is based on the classical DES (Data Encryption Standard) design. This approach makes it possible to considerably decrease chip size requirements.

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거주자 요구를 고려한 수납면적에 관한 연구 (A Study on planning of storage area considering residents' needs)

  • 이세나;이현수
    • 한국실내디자인학회:학술대회논문집
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    • 한국실내디자인학회 2006년도 춘계학술발표대회 논문집
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    • pp.193-196
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    • 2006
  • The storage style has changed because of diversity of family types, improvement of cost of living, and increase of leisure time. In spite of this change, storage space has still caused discomfort since it did not consider residents' convenience. Therefore, in this study, Brand Apartments were selected, furniture detail drawing was analyzed by plan of housing size and zone to calculate storage area and capacity, and finally needs of storage space were analyzed using survey. Satisfaction of storage space was generally low and $20{\sim}30%$ increase of storage space was demanded. The reasons why the storage space was not satisfied are followed. First, storage space was insufficient. Second, the inner structure of storage space was unified. According to change of life style, needs have changed. To satisfy these needs, the inner division of storage space is planned with considering various items. In addition, development of hardware, flexible division, and priority of storage space with considering user's convenience are needed.

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Designing Intervention Arthritis Self-Management Program with Tai Chi for Older Adults with Osteoarthritis in Rural Korea

  • So, Aeyoung;Park, Sunah
    • International journal of advanced smart convergence
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    • 제7권2호
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    • pp.55-66
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    • 2018
  • Osteoarthritis is one of the most common chronic degenerative disease and prevalent among women in rural area. A variety of self-management programs for arthritis patients have been developed and administered, however the effectiveness and adherence to the program including arthritis exercise are found to be low. The purpose of this study is to design intervention Arthritis Self-Management Program with Tai Chi (ASMP-TC) through identifying and analyzing attributes influencing adherence exercise behavior in Korean older adult women with arthritis in rural area. For this, the existing and relevant evidence on arthritis self-management including exercise intervention were investigated, and then this study describes well-designed arthritis self-management program to provide the credibility and validity necessary for its interventions. In addition, this study try to propose a self-management program model of Tai Chi exercise for rural older adults to improve adherence based on the primary health care facility, which is vulnerable area in Korea.

대면적 플랫폼을 갖는 Probe-based Storage Device(PSD)용 정전형 2축 MEMS 스테이지의 설계 (Design of an Electrostatic 2-axis MEMS Stage having Large Area Platform for Probe-based Storage Devices)

  • 정일진;전종업
    • 한국공작기계학회논문집
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    • 제15권3호
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    • pp.82-90
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    • 2006
  • Recently the electrostatic 2-axis MEMS stages have been fabricated for the purpose of an application to PSD (Probe-based Storage Device). However, all of the components(platform, comb electrodes, springs, anchors, etc.) in those stages are placed in-plane so that they have low areal efficienceis, which is undesirable as data storage devices. In this paper, we present a novel structure of an electrostatic 2-axis MEMS stage that is characterized by having large area platform. for obtaining large area efficiency, the actuator part consisting of mainly comb electrodes and springs is placed right below the platform. The structure and operational principle of the MEMS stage are described, followed by a design procedure, structural and modal analyses using FEM(Finite Element Method). The areal efficiency of the MEMS stage was designed to be about 25%, which is very large compared with the conventional ones having a few percentage.

부분 재구성 방법을 이용한 재구성형 FIR 필터 설계 (Implementation of a FIR Filter on a Partial Reconfigurable Platform)

  • 최창석;오영재;이한호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.531-532
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    • 2006
  • This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

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LID-IMPs 선정 가이드라인 제시와 아파트단지에서의 LID 설계 (Guideline of LID-IMPs Selection and the Strategy of LID Design in Apartment Complex)

  • 전지홍;김정진;최동혁;한재웅;김태동
    • 한국물환경학회지
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    • 제25권6호
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    • pp.886-895
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    • 2009
  • The guideline of selection of Integrated Management Practices (IMPs), such as wood, green roof, lawn, and porous pavement, for Low Impact Development (LID) design was proposed by ranking the reduction rate of surface runoff using LIDMOD1.0. Based on the guideline, LID was designed with several scenarios at two apartment complexes located at Songpa-gu, Seoul, Korea, and the effect of LID on surface runoff was evaluated during last 10 years. The effect of runoff reduction of IMP by land use change was highly dependent on the kind of hydrologic soil group. The wood planting is the best IMPs for reduction of surfac runoff for all hydrologic soil groups. Lawn planting is an excellent IMP for hydrologic soil group A, but reduction rate is low where soil doesn't effectively drains precipitation. The green roof shows constant reduction rate of surface runoff because it is not influenced by hydrologic soil group. Compared to the rate of other IMPs, the green roof is less effect the surface runoff reduction for hydrologic soil group A and is more effect for hydrologic soil group C and D followed to planing wood. The porous pavement for the impervious area is IMPs which is last selected for LID design because of the lowest reduction rate for all hydrologic soil group. As a result of LID application at study areas, we could conclude that the first step of the strategy of LID design at apartment complex is precuring pervious land as many area as possible, second step is selecting the kind of plant as more interception and evapotranspiration as possible, last step is replacing impervious land with porous pavement.

전류 재사용 기법을 이용한 저전력 CMOS LNA 설계 (Design of Low Power CMOS LNA for using Current Reuse Technique)

  • 조인신;염기수
    • 한국정보통신학회논문지
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    • 제10권8호
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    • pp.1465-1470
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    • 2006
  • 본 논문에서는 단거리 무선 통신의 새로운 국제 표준으로 부상하고 있는 2.4 GHz ZigBee 응용을 위한 저전력 CMOS LNA(Low Noise Amplifier)를 설계하였다. 제안한 구조는 전류 재사용 기법을 이용한 2단 cascade구조이며 회로의 설계에서 TSMC $0.18{\mu}m$ CMOS 공정을 사용하였다. 전류 재사용단은 두 단의 증폭기 전류를 공유함으로써 LNA의 전력 소모를 적게 하는 효과를 얻을 수 있다. 본 논문에서는 LNA설계 과정을 소개하고 ADS(Advanced Design System)를 이용한 모의실험 결과를 제시하여 검증하였다. 모의실험 결과, 1.0V의 전압이 인가될 때 1.38mW의 매우 낮은 전력 소모를 확인하였으며 이는 지금까지 발표된 LNA 중 가장 낮은 값이다. 또한 13.83dB의 최대 이득, -20.37dB의 입력 반사 손실, -22.48dB의 출력 반사 손실 그리 고 1.13dB의 최소 잡음 지수를 보였다.

Automatic Pattern Setting System Reacting to Customer Design

  • Yuan, Ying;Huh, Jun-Ho
    • Journal of Information Processing Systems
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    • 제15권6호
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    • pp.1277-1295
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    • 2019
  • With its technical development, digital printing is being universally introduced to the mass production of clothing factories. At the same time, many fashion platforms have been made for customers' participation using digital printing, and a tool is provided in platforms for customers to make designs. However, there is no sufficient solution in the production stage for automatically converting a customer's design into a file before printing other than designating a square area for the pattern designed by the customer. That is, if 30 different designs come in from customers for one shirt, designers have to do the work of reproducing the design on the clothing pattern in the same location and in the same angle, and this work requires a great deal of manpower. Therefore, it is necessary to develop a technology which can let the customer make the design and, at the same time, reflect it in the clothing pattern. This is defined in relation to the existing clothing pattern with digital printing. This study yields a clothing pattern for digital printing which reflects a customer's design in real time by matching the diagram area where a customer designs on a given clothing model and the area where a standard pattern reflects the customer's actual design information. Designers can substitute the complex mapping operation of programmers with a simple area-matching operation. As there is no limit to clothing designs, the variousfashion design creations of designers and the diverse customizing demands of customers can be satisfied at low cost with high efficiency. This is not restricted to T-shirts or eco-bags but can be applied to all woven wear, including men's, women's, and children's clothing, except knitwear.

IEEE 802.11a OFDM 타이밍 동기화기 블록의 저면적 설계 및 구현 (Low Area Design and Implementation for IEEE 802.11a OFDM Timing Synchronization Block)

  • 석상철;장영범
    • 대한전자공학회논문지SD
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    • 제49권2호
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    • pp.31-38
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    • 2012
  • 이 논문에서는 IEEE 802.11a OFDM MODEM SoC용 타이밍 동기화 블록에 대한 저면적 구조를 제안한다. IEEE 802.11a의 타이밍 동기화 블록은 큰 구현 면적을 필요로 한다. 제안된 자기 상관 방식의 타이밍 동기화 블록 구조는 전치 직접형 필터 구조를 사용하여 곱셈 연산을 최소화하였다. 또한 CSD(Canonic Signed Digit) 계수를 이용하는 기술과 Common Sub-expression Sharing 기술을 적용하여 곱셈연산을 저면적으로 구현하였다. 제안된 타이밍 동기화 블록 구조에 대하여 Verilog-HDL 코딩과 0.13 micron 공정을 사용하여 합성한 결과, 기존 구조와 비교하여 22.7%의 구현 면적 감소 효과를 얻을 수 있었다.