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Low Area Design and Implementation for IEEE 802.11a OFDM Timing Synchronization Block  

Seok, Sang-Chul (Dept. of Information Technology, SangMyung University)
Jang, Young-Beom (Dept. of Information Technology, SangMyung University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.2, 2012 , pp. 31-38 More about this Journal
Abstract
In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.
Keywords
OFDM; timing synchronization; frequency offset synchronization; Canonic signed Digit(CSD);
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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