• 제목/요약/키워드: low voltage implementation

검색결과 217건 처리시간 0.026초

단상 액티브 파워 필터를 위한 새로운 전류 보상 방법 (A New Current Compensation Estimation Method For Single Phase Active Power Filter)

  • 곽상신;이무영
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.819-822
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    • 1998
  • A new active power filter (APF) circuit with a current compesation estimation method is proposed. The current compensation estimation method replaces a current sensor with an estimating circuit and therefore reduces the implementation cost In addition, a simple control scheme, based on the energy balance concept, is adopted to control the voltage of a DC capacitor. Therefore energy change in the DC capacitor can be compensanted in the next cycle. Since a sampling technique is used, a larger DC capacitor voltage ripple can be permissible and a relatively smaller DC capacitor can be used. The proposed method has advantages of the reduction of one current sensor, low implementation cost, and fast transient responses. The theoretical analysis and simulation results are given. The proposed control method is successfully verified by computer simulation.

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비검출 전류 제어기를 사용한 3상 전압형 PWM CONVERTER 구현 (Implementation of a 3 Phase Voltage-Sourced PWM Converter Using the Sensorless Input Current Controller)

  • 강동구;이우철;권성곤
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 하계학술대회 논문집 F
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    • pp.2210-2212
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    • 1997
  • A sensorless input current controller for three phase PWM converter is proposed. A merit of this controller is that sinusoidal input line current, unity power factor, and ripple-free DC voltage can be achieved with low-cost. The paper describes the proposed control strategy and its implementation. Simulation result for the proposed controller is compared with that of the sensor based version.

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DSP를 이용한 부스트 컨버터의 전류 제어기 설계 및 구현 (Design and Implementation of a Current Controller for Boost Converters Using a DSP)

  • 이광운
    • 전력전자학회논문지
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    • 제17권3호
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    • pp.259-265
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    • 2012
  • This paper introduces a method for design and implementation of a current controller for boost converter operating in continuous conduction mode (CCM) using a digital signal processor (DSP). A Proportional-Integral (PI) type current controller outputs an average voltage command for inductor, used in the input side of the boost converter, and the duty-ratio of PWM (pulse width modulation) signal for switching device is directly calculated from the average voltage command. The gains of the PI current controller are selected such that the current response characteristics are the same as those of a first-order low-pass filter. The proposed current control scheme is implemented using a DSP based on fixed-point math operations and an experimental study has been performed to validate the proposed method.

배전용 반도체 변압기 구현을 위한 SiC MOSFET 기반 전력변환회로 단위모듈 설계에 관한 연구 (Design and Implementation of a Power Conversion Module for Solid State Transformers using SiC MOSFET Devices)

  • 임정우;조영훈
    • 전력전자학회논문지
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    • 제22권2호
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    • pp.109-117
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    • 2017
  • This paper describes the design and implementation of a unit module for a 10 kVA class 13.2 kV/220 V unidirectional solid-state transformer (SST) with silicon-carbide metal-oxide-semiconductor field-effect transistors. The proposed module consists of an active-front-end (AFE) converter to interface 1320 V AC voltage source to 2500 V DC link and an isolated resonant DC-DC converter for 500 V low-voltage DC output. The design approaches of the AFE and the isolated resonant DC-DC converters are addressed. The control structures of the converters are described as well. The experiments for the converters are performed, and results verify that the proposed unit module can be successfully adopted for the entire SST operation.

Voltage Feedforward Control with Time-Delay Compensation for Grid-Connected Converters

  • Yang, Shude;Tong, Xiangqian
    • Journal of Power Electronics
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    • 제16권5호
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    • pp.1833-1842
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    • 2016
  • In grid-connected converter control, grid voltage feedforward is usually introduced to suppress the influence of grid voltage distortion on the converter's grid-side AC current. However, owing to the time-delay in control systems, the suppression effect of the grid voltage distortion is seriously affected. In this paper, the positive effects of the grid voltage feedforward control are analyzed in detail, and the time-delay caused by the low-pass filter (LPF) in the voltage filtering circuits and digital control are summarized. In order to reduce the time-delay effect on the performance of the feedforward control, a voltage feedforward control strategy with time-delay compensation is proposed, in which, a leading correction of the feedforward voltage is used. The optimal leading step used in this strategy is derived from analyzing the phase-frequency characteristics of a LPF and the implementation of digital control. By using the optimal leading step, the delay in the feedforward path can be further counteracted so that the performance of the feedforward control in terms of suppressing the influence of grid voltage distortion on the converter output current can be improved. The validity of the proposed method is verified through simulation and experiment results.

Fast Voltage-Balancing Scheme for a Carrier-Based Modulation in Three-Phase and Single-Phase NPC Three-Level Inverters

  • Chen, Xi;Huang, Shenghua;Jiang, Dong;Li, Bingzhang
    • Journal of Electrical Engineering and Technology
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    • 제13권5호
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    • pp.1986-1995
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    • 2018
  • In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

소프트웨어 전압 제어를 사용한 저전력 VLSI 시스템의 설계 및 구현 (Design and implementation of low-power VLSI system using software control of supply voltages)

  • 이성수
    • 대한전자공학회논문지SD
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    • 제39권4호
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    • pp.72-83
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    • 2002
  • 본 논문에서는 공급 전압을 순수하게 소프트웨어적으로 제어함으로서, 하드웨어 구현이 간단하고 전력 소모를 효과적으로 줄이며 복잡한 인터페이스 회로가 필요 없는 새로운 저전력 VLSI 시스템 아키텍처를 제안하였다. 제안된 아키텍처는 클록 주파수-공급 전압 특성을 순수하게 소프트웨어적으로만 모델링하고, 시스템상의 여러 칩들에 대해서 각각 독립적으로 공급 전압을 제어하고, 주 클록 주파수 f/sub CLK/의 1/n인 f/sub CLK/, f/sub CLK/2, f/sub CLK/3...만을 클록 주파수로 허용하였다. 또한, 제안된 저전력 VLSI 시스템 아키텍처의 프로토타입 시스템을 제작하고 전력 소모를 측정하였다. 프로토타입 시스템은 기존의 상용 마이크로프로세서 평가 보드를 약간 수정하여 레벨 쉬프터와 전안 스위치와 같은 간단한 개별 소자만을 덧붙여서 제작되었으며, 0.58W이던 전력 소모가 0.12W로 감소함을 확인할 수 있었다.

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

  • Kwon, Youngsu;Lee, Jae-Jin;Shin, Kyoung-Seon;Han, Jin-Ho;Byun, Kyung-Jin;Eum, Nak-Woong
    • IEIE Transactions on Smart Processing and Computing
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    • 제4권2호
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    • pp.71-77
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    • 2015
  • Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

병렬제어기법이 적용된 1.8kW급 마일드 하이브리드 양방향 LDC 설계 및 구현 (Design and Implementation of 1.8kW bi-directional LDC with Parallel Control Strategy for Mild Hybrid Electric Vehicles)

  • 김현빈;정재웅;배성우;김종수
    • 전력전자학회논문지
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    • 제22권1호
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    • pp.75-81
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    • 2017
  • This paper presents a design and parallel control strategy of 1.8 kW low-voltage DC-DC converter (LDC) for mild hybrid electric vehicles to improve their power density, system efficiency, and operation stability. Topology and control scheme are important on the LDC for mild hybrid electric vehicles to achieve high system efficiency and power density because of their very low voltage and large current in input and output terminals. Therefore, the optimal topological structure and control algorithm are examined, and a detailed design methodology for the power and control stages is presented. A working sample of 1.8 kW LDC is designed and implemented by applying the adopted topology and control strategy. Experimental results indicate 92.45% of the maximum efficiency and 560 W/l of power density.

Digital Front-End Design에서의 반도체 특성 연구 및 방법론의 고찰 (Semiconductor Characteristics and Design Methodology in Digital Front-End Design)

  • 정태경;이장호
    • 한국정보통신학회논문지
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    • 제10권10호
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    • pp.1804-1809
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    • 2006
  • 본 고에서는 디지털 회로의 저 전력소모의 설계와 구현에 관련된 디지털 전대역 회로 설계를 통해서 전반적인 전력 소모의 방법론과 이의 특성을 고찰하고자 한다. 디지털 집적회로의 설계는 광대하고 복잡한 영역이기에 우리는 이를 저전력 소모의 전반적인 회로 설계에 한정할 필요가 있다. 여기에는 로직회로의 합성과, 디지털 전대역 회로설계에 포함되어 있는 입력 clock 버퍼, 레치, 전압 Regulator, 그리고 케페시턴스와 전압기가 0.12 마이크론의 기술로 0.9V의 전압과 함께 쓰여져서 동적 그리고 정적 에너지 소모와 압력, 가속, Junction temperature 등을 모니터 할 수 있게 되어 있다.