• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• Journal of Power Electronics
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• v.12 no.3
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.11
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• pp.1800-1805
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• 2016

The micro-grid designed as bipolar ${\pm}750V$ low-voltage DC power distribution system demonstrated by KEPRI, demands interconnection of a number of small decentralized power source including variable renewable generator. Therefore, variable researches for the influence of interconnection with the bipolar typed DC grid and these variable power sources are required for superior quality of power distribution. Renewable power generation simulators for the bipolar ${\pm}750V$ low-voltage DC power distribution system are necessary for such researches. In this paper, we carry out a research on the photovoltaic simulator that be actually able to interconnect with a bipolar ${\pm}750V$ low-voltage micro-grid. Simulator for this research is not only able to simulate photovoltaic generation according to weather informations and PV modules characteristics, but also contribute to stabilization of bipolar ${\pm}750V$ low-voltage of the system. Therefore, the simulator was designed to develop a system that can situationally respond to variable control algorithms such as the MPPT control, droop control, EMS power control, etc.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.1
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• pp.54-60
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• 2006

A power limiting algorithm is proposed for stable operation of grid-connected inverter in case of grid voltage unbalance considering the operation limit of inverter. During the voltage unbalance the control performance of Inverter. is degraded and the output power contains 120Hz ripple due to the negative sequence of voltage. In this paper, conventional dual sequence current controller is implemented to solve these problems using separated control of positive and negative sequence. Especially the maximum power limit which guarantees the maximum rated current of the inverter is automatically calculated as the instant grid voltage changes. As soon as the voltage recovers the proposed algorithm can return to the normal power control mode accomplishing low voltage ride through. Proposed algorithm is verifed using PSCAD/EMTDC simulations and tested experimentally at 4.4kW wind turbine simulator set-up.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.159-166
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• 2010

For a grid-connected inverter in distributed generation systems, the current control is essential, and recently, the predictive current control based on a high performance digital signal processors (DSP) to satisfy a fast dynamic response has been widely investigated. However, the performance of predictive current control is degraded by the time delay due to digital implementation, the parameter and measured value errors and the interference of noise, and also theses make system even unstable. Therefore, this paper proposes the predictive current control using grid voltage observer for grid-connected inverter applications. To determine the relevant voltage observer gain, the low-order harmonics of grid voltage are considered, and the effect of filter parameter errors is analyzed. The proposed method has a fast current response capability, the robustness to noise and simple implementation due to voltage sensorless control and the robust current control performance to low-order grid harmonics. The feasibility of the proposed method is verified by simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.1
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• pp.102-107
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• 2005

This paper describes a new voltage sag-swell generator for the test of custom power devices such as UPS, DVR, DSTATCOM, SSTS, etc. Voltage sag, swell, outage, and unbalance generation mechanism and the operating principle are described for the proposed scheme. The usefulness of the scheme is proved through simulations and experiments. The proposed scheme has good features of simple structure, high reliability, wide range of sag and swell variation, and easy control. Especially, the scheme can provide a cost-effective implementation of a power quality disturbance generator. Therefore, it is expected that the scheme will contribute to the self implementation of the system with low cost in laboratory.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1407-1414
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• 2016

Unlike existing pulse-width modulation (PWM) techniques, such as sinusoidal PWM and random PWM, the wavelet PWM (WPWM) technique based on a Harr wavelet function can achieve a high fundamental component for the output voltage, low total harmonic distortion, and simple digital implementation. However, the original WPWM method lacks output voltage control. Thus, the practical application of the WPWM technique is limited. This study proposes an improved WPWM technique that can regulate output voltage amplitude with the addition of a parameter. The relationship between the additional parameter and the output voltage amplitude is analyzed in detail. Experimental results verify that the improved WPWM exhibits output voltage control in addition to all the merits of the WPWM technique.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.543-550
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• 2008

This paper proposes an voltage and reactive power control methodology, which is motivated towards implementation in the korea power system. The main voltage control devices are capacitor banks, reactor banks and LTC transformers. Effects of control devices are evaluated by local subsystem's cost computations. This local subsystem is decided by 'Tier' and 'Electrical distance' in the whole system. The control objective at present is to keep the voltage profile within constraints with minimum switching cost. A robust control strategy is proposed to make the control feasible and optimal for a set of power-flow cases that may occur important event from system. This studies conducted for IEEE 39-bus low and high voltage contingency cases indicate that the proposed control methodology is much more effective than PSS/E simulation tool in deciding switching of capacitor and reactor banks.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.948-950
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• 2003

In this literature, the CMOS current mode fout quadrant differentiator circuit is proposed. The implementation is base on an appropriate input stage that converts the input current into a compressed voltage at the input capacitor ($C_{gs}$) of the CMOS driver circuit. This input voltage use as the control output current which flow to the output node by passing through a MOS active load and use it as the feedback voltage to the input node. Simulation results with level 49 CMOS model of MOSIS are given to demonstrate the correct operation of the proposed configuration. But the gain of the circuit is too low so the output differentiate current also low. The proposed differentiator is expected to find several applications in analog signal processing system.