• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.60-68
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• 2007

A technique is presented to extract differential second harmonic output from common source nodes of a cross-coupled P-& N-FET oscillator. Provided the impedances at the common source nodes are optimized and the fundamental swing at the VCO core stays in a proper mode, it is found that the amplitude and phase errors can be kept within $0{\sim}1.6dB$ and $+2.2^{\circ}{\sim}-5.6^{\circ}$, respectively, over all process/temperature/voltage corners. Moreover, an impedance-tuning circuit is proposed to compensate any unexpectedly high errors on the differential signal output. A Prototype 5-GHz VCO with a 2.5-Hz LC resonator is implemented in $0.18-{\mu}m$ CMOS. The error signal between the differential outputs has been measured to be as low as -70 dBm with the aid of the tuning circuit. It implies the push-push outputs are satisfactorily differential with the amplitude and phase errors well less than 0.34 dB and $1^{\circ}$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.230-238
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• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.666-672
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• 2014

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

• Korean Journal of Applied Biomechanics
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• v.17 no.2
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• pp.1-9
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• 2007

Walking is not only an essential component of the human mobility, but also is a good exercise. Inability to walk freely can reduce an individual's quality of life and independence substantially. Being a relatively low impact activity, walking is particularly good for the elderly and research has shown that regular walking in the elderly reduces the chance of fall-related injuries and mental diseases as well. In spite of the documented benefits of regular walking, it is still difficult to walk without the aid of assistive devices for the frail elderly who have lower extremity problems. Assistive walking devices(AWD), such as crutches, canes, hiking-poles, T-Poles and walkers, are often prescribed to the elderly to make their walking be safe and efficient. Many researchers have demonstrated the effects of AWDs such as reducing lower extremity loading, improved dynamic/gait stability, yet, no study has been done for gait pattern when the elderly gait with AWDs. Therefore, the purpose of this study was to examine whether T-Poles, one of the AWDs, change the elderly gait pattern. Eight community-dwelling female elderly participated in this study. Laboratory kinematics during walking with T-Poles(PW) and with out T-Poles(NPW) was assessed. PW showed significant increase in step width, stride length, gait velocity and decrease in swing time. No significances were found in lower body joint angles but meaningful trend and pattern were found. Maybe the reason was due to the participants. Our participants were healthy enough so that the effect of T-Poles was minimum. PW also showed typical gait phases which are no single support phase during a gait cycle. It indicates that walking with T-Poles may guarantee safe and confident walking to the frail elderly.

• Korean Journal of Applied Biomechanics
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• v.13 no.3
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• pp.163-180
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• 2003

This paper aims at collecting the guantitative data of kenematic variables by analysing the gait patterns of the normal adult men and the handicapped. The gait motions were taped with 4 video cameras, the cinematographic analyses were performed by the DLT technique of three dimensional image treatment. The following results were obtained in the analysis of the variables: 1. The ratio of stance time and swing time did not show any significant difference in the groups of the normal men and the handicapped when both foot of the former and the right feet of the latter were compared. The stride peeriod time of these two groups were 1.12 and 1.11 second, respectively. 2. In the handicapped group, the step width was wider, the step length and stride length were shorter, and especially, the step length of the right foot was shorter, 3. The small vertical displacement of left toes of the handicapped group showed that the heal contact and the left midstance are almost simultaneous. 4. The two groups have almost the same horizontal displacement of the center of gravity and the same vertical rate of extension. In view of the velocity of the center of gravity the normal adults showed the constant speed of movement. However, the handicapped adults were reduced from the right midstance to the right toe-off. 5. The handicapped showed prominently low angle on the left toe-off in the ankle joint angle, they also had the tendency to walk in the patterns of extended knee in the knee joint angle. Both the handicapped and the normal had the hyperextension on the toe-off in the hip joint angle. In the back and front angle of body, both showed the slightly back-sided walking positions. 6. Both groups had the abduction of both feet in foot placement angle, but the handicapped did not show serious abduction of left midstance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1310-1318
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• 1998

Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.