• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.99-105
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• 2004

A shared-capacitor charge-sharing ROM (SCCS-ROM) using dummy bit lines is proposed. The SCCS-ROM reduces the bit line swing voltage using the charge-sharing technique of the conventional charge-sharing ROM (CS-ROM). Although the CS-ROM needs three small capacitors per output bit, the proposed SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only increases noise immunity but also reduces power. A SCCS-ROM with 8K${\times}$15bits implemented in a 0.35${\mu}{\textrm}{m}$ CMOS process. The SCCS-ROM consumes 8.63㎽ at 100MHz with 3.3V The simulation results show that the SCCS-ROM reduces 8.4% power compared to the CS-ROM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.163-168
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• 2014

Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of $0.1135cm^2/V{\cdot}s$, ${\sim}10^6$, 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at $300^{\circ}C$, $350^{\circ}C$, and $400^{\circ}C$ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.05a
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• pp.780-785
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• 2003

Recently the trends in information storage devices need small size, mobility, high capacity, and low power consumption etc. To satisfy those, the development of high performance actuator is an important issue. Compared with general linear actuator for optical disk drive, swingarm type rotary actuator is suitable to design in small form factor and has fast access time for random access. Swingarm actuator is designed considering the structural problem and the actuating force of VCM(Voice Coil Motor). The increase of mass caused by optical components makes vibration problems of swing-arm, therefore resonance frequency should be increased and inertia has to be reduced. ANSYS FEM tool is employed in optimizing swingarm. The VCM is designed using 3-D electro-magnetic analysis, and parameters of magnetic circuit are determined to matte large flux density. The large flux density enables to achieve low power consumption. VCM holder is designed to get the mass balance of total actuator and this balance reduces the magnitude of critical mode relative to pivot bearing, It is expected that swingarm type rotary actuator designed by this method is available to variable type of micro optical disk drives.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.575-581
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• 2013

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

• Korean Journal of Applied Biomechanics
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• v.15 no.3
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• pp.61-70
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• 2005

The purpose of study was to investigate the kinematic variables of Kenmotsu motion in Parallel bars. To this study, by 3 dimensional kinematical analysis of 4 male national gymnasts participants in the 28th Athens Olympic Game in 2004, kinematic data collected using video camera. Coordinate data were smoothed by using a fourth-order Butterworth low pass digital filter with cutoff frequency of 6Hz. The conclusions were as follows. 1. In P2, because the constrained swing movement made the movement of a rising back difficult7, the movements of Reg. were performed at low position after Air phase. 2. In E5 event, for the shake of a stable handstand and applied techniques like a Belle(E-value), a Belle Piked(super E-value), a vertical velocity in E2, a horizontal velocity in E3 and a vertical velocity in E4 were necessary for high velocities. 3. In E4 event, it was appeared that for a flexible body's movement of a vertical up-flight, the large angle of the shoulder joint and the flexion & extension of the hip joint were necessary in Air phase and a long flight time and vertical displacement made Reg. movements stable at the high position.