• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.91-96
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• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.417-422
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• 2015

A 6.5 - 8.5 GHz CMOS UWB transmitter is implemented using $0.18{\mu}m$ CMOS technology. The transmitter is mainly composed of switched LC VCO and digital pulse generator (DPG). Using RF switch and DPG, the uniform power and sidelobe rejection are achieved irrespective of the carrier frequency. The measured UWB carrier frequency range is 7 ~ 8 GHz and the pulse width is tunable from 1 to 2 ns. The measured energy efficiency per pulse is 2.1 % and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier. The chip core size is $0.72mm^2$.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.47-55
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• 1996

An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.221-228
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• 2011

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a$ 0.18-{\mu}m$ CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 $mm^2$ of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 ${\mu}A$ and 40 ${\mu}A$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.35-40
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• 2012

This paper has proposed a 3~5 GHz IR-UWB low power transmitter for range detection application. Proposed transmitter which has been implemented in a $0.13{\mu}m$ CMOS technology is all digital circuit that consist of simple digital logic. this feature insure low complexity and low power consumption. In addition, center frequency can be changed by adopting voltage controlled delay cell for avoiding existing another radio frequency in UWB low band. Proposed circuit consume only 10pJ/b from 1.2 V supply voltage. The simulation results show 3.3~4.3 GHz center frequency controllability, -51 dBm/MHz maximum output power and is satisfied with FCC regulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.853-862
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• 2019

In this paper, we designed a 4.5kW X-band SSPA transmitter to replace the TWTA search radar transmitter with low MTBF and high maintenance cost. The transmitter is designed for the performance of over 520W average transmission output and 4.0kW maximum transmission output. In particular, by implementing a graceful degradation, it is designed to maintain better performance than conventional TWTA transmitter up to 40% (13 assembly modules) failure level of 200W power amplifier assembly. Through an experiment on the effective range of X-band, the performance of proposed transmitter verified the values of the maximum transmission output 6.1kW, spurious output 69.16dBc, RF pulse rising time 15.2ns and RF pulse falling time 16.3ns. The experiment confirmed the change of output power according to the graceful degradation due to fault injection.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1134-1136
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• 2002

This paper proposes a FSK(Frequency Shift Keying) transmitter which has a inverter for power amplification instead of linear amplifier. As it can generate large signal using resonant circuit under the low voltage source even if the impedance of antenna is large as like a loop antenna of TWC(Train to Way-side Communication) system. In this paper, the proposed fully digital controlled transmitter including FSK modulation is presented and its control schemes are discussed.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.43-49
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• 2014

This paper presents a theoretical study of transmission performance for an optical duobinary transmitter employed a Mach-Zehnder modulator and a electrical low pass filter at 40Gbps optical communication links. It depends on the bandwidth of the low pass filter in the transmitter, the optical filter and the filter in the receiver. Also, each filter affected to the various parts of the optical power spectrum. By optimizing the bandwidth of each filter, we could control the side robes and the ripples and improve the dispersion tolerance of the transmission system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.