• 대한전자공학회논문지SD
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• 제41권5호
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• pp.61-70
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• 2004

뉴럴 네트워크는 동작 모드를 학습과 인지 과정으로 구분할 수 있다. 학습은 다양한 입력 패턴에 대하여 학습자가 원하는 결과값을 얻을 때까지 결합계수를 업데이트하는 과정이고, 인지는 학습을 통해 결정된 결합계수와 입력 패턴과의 연산을 수행하는 과정이다. 기존의 내적연산 프로세서는 처리 속도를 개선하고 하드웨어 복잡도를 줄이는 다양한 구조가 연구되었지만 뉴럴 네트워크의 학습과 인지모드에 대한 차별화된 구조는 없었다. 이를 위해, 본 논문에서는 재구성 가능한 뉴럴 네트워크 구현을 위한 새로운 저전력 내적연산 프로세서 구조를 제안한다. 제안한 구조는 학습모드에서 기존의 비트-시리얼 내적연산 프로세서와 같이 동작을 하여, 비트-레벨의 타른 처리 및 하드웨어 구현에 적합하고 높은 수준의 파이프라인 적용이 가능하다는 장점을 가진다. 또한, 인지모드에서는 고정된 결합계수에 따라 연산을 수행할 활성화 유닛을 최소화시킴으로서 전력 소비를 줄일 수 있다. 시뮬레이션 결과 활성화 유닛은 결합계수에 의존적이기는 하지만 50% 내외까지 줄일 수 있음을 확인하였다.

• 센서학회지
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• 제27권1호
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.301-303
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• 2001

In this paper we present a Capacitor Charging Power Supply (CCPS) using a series-resonant three-level inverter topology to improve voltage regulation and use semiconductor switches having low blocking voltage capability such as MOSFETs. This inverter can be operated with two modes, Full Power Mode (FPM) and Half Power Mode (HPM). In FPM inverter supplies the high frequency step up transformer with full DC-link voltage and in HPM with half DC-link voltage. HPM switching method will be adopted when CCPS output voltage reaches the preset target value and operates in refresh mode-charge is maintained on the capacitor. In this topology each semiconductor devices blocks a half of the DC-link voltage[2]. A 15kW, 30kV CCPS has been built and will be tested for an electric precipitator application. The CCPS operates from an input voltage of 500VDC and has a variable output voltage between 10 to 30kV and 1kHz repetition rate at 44nF capacitive load [3]. A resonant frequency of 67.9kHz was selected and a voltage regulation of $0.83\%$ has been achieved through the use of half power mode without using the forced cut off the switch current [1]. The theory of operation, circuit topology and test results are given.

• 전력전자학회논문지
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• 제14권4호
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• pp.299-306
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• 2009

최근 대기전력저감기능을 갖는 PWM IC를 적용한 플라이백 컨버터는 대기전력 모드 시 Burst 스위칭 동작에 의해 전력소모를 최소화 할 수 있지만 경 부하 및 대기전력모드 시 변압기를 통해 흐르는 큰 자화전류에 의해 여전히 낮은 효율특성을 가지는 문제점이 있었다. 본 논문에서는 경 부하 및 대기전력모드 동작 시 자화전류를 최 소화함으로 효율을 개선한 회로를 제안하였으며 50인치 PDP TV PSU (Power Supply Unit)에 있어서 대기전력 및 보조전원으로 사용된 70W 플라이백 컨버터에 적용 실험하여 보았다.

• 한국전자통신학회논문지
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• 제3권2호
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• pp.86-92
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• 2008

고속 데이터 전송이 가능한 장점 때문에 OFDM 통신 방식은 4세대 통신 방식으로 주목 받고 있다. OFDM은 이러한 고속 무선 데이터 통신을 구현하기 위해서는 고성능의 FFT(Fast-Fourier-Transform) / IFFT(Inversion FFT) 프로세서를 필요로 한다. 현재 OFDM은 DSP(Digital Signal Processor)로 구현되고 있지만 많은 전력 소모의 단점을 가지고 있다. 이러한 단점을 보완하기 위해 Current-mode FFT LSI가 제안되었다. 본 논문에서는 저전력 OFDM용 IVC(Current to Voltage Converter)를 설계한다. 시뮬레이션 결과 설계된 IVC는 FFT Block의 출력이 $7.35{\mu}A$ 이상일 때 3V 이상의 전압을 출력하고, FFT Block의 출력이 $0.97{\mu}A$ 이하일 때 0.5V 이하의 전압을 출력하였다. 설계된 IVC로 저전력 Current-mode FFT LSI의 동작이 가능하게 되며, 전류모드신호처리는 차세대 무선 통신 시스템의 발전에 기여할 것이다.

• 한국멀티미디어학회논문지
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• 제23권2호
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• pp.293-300
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• 2020

Since the communication networks like the Internet collapses at disaster and calamity sites, a maintenance system that can be operated offline is required for the maintenance of various facilities. In this paper, we propose a system that memory tags attached on the facilities may transmit the emergency manual to a smart-phone, and the smart phone displays it off-line. The main issue is to design low energy mode memory tags. This study presents two kinds of methods and analyzes each's energy consumption mode. The first one is to develop memory tags by using one chip, and the next one is to design memory tags by forming multi-modules. Both ways show proper application fields under the low energy mode. This research selects the off-line maintenance system by using one chip design, and proposes the direction of contents for enhancing the effectiveness of the system. And we expect that this memory tags will be valuable for disaster scenes as well as battle fields.

• Journal of Power Electronics
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• 제18권1호
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• pp.11-22
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• 2018

This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for renewable energy applications. The proposed converter is composed of a coupled inductor, a passive clamp circuit, a switched capacitor and voltage lift circuits. The passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The configuration of the passive clamp and switched capacitor circuit increases the voltage gain. A wide continuous conduction mode (CCM) operation range, a low turn ratio for the coupled inductor, low voltage stress on the switch, switch turn on under almost zero current switching (ZCS), low voltage stress on the diodes, leakage inductance energy recovery, high efficiency and a high voltage gain without a large duty cycle are the benefits of this converter. The steady state operation of the converter in the continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is discussed and analyzed. A 200W prototype converter with a 28V input and a 380V output voltage is implemented and tested to verify the theoretical analysis.

• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Journal of Power Electronics
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• 제18권4호
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• pp.985-996
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• 2018

The implementation and performance evaluation of an interleaved boundary conduction mode (BCM) boost power factor correction (PFC) converter is presented in this paper by employing three wide band-gap switching devices: a super junction silicon (Si) MOSFET, a silicon carbide (SiC) MOSFET and a gallium nitride (GaN) high electron mobility transistor (HEMT). The practical considerations for adopting wide band-gap switching devices to BCM boost PFC converters are also addressed. These considerations include the gate drive circuit design and the PCB layout technique for the reliable and efficient operation of a GaN HEMT. In this paper it will be shown that the GaN HEMT exhibits the superior switching characteristics and pronounces its merits at high-frequency operations. The efficiency improvement with the GaN HEMT and its application potentials for high power density/low profile BCM boost PFC converters are demonstrated.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.147-148
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• 2011

In this paper, implementation of digital control for critical conduction mode power factor correction (PFC) rectifier is presented. Critical conduction mode is widely used in medium and low power conversion application due to its minimized MOSFET turn-on loss and diode reverse-recovery problem. However, it needs additional zero current detection circuit and maximum frequency limit to properly turn the MOSFET on and avoid the excessive switching loss in light load operation. This paper explains the digital IC implementation and verifies its operation with 200-W prototype PFC rectifier.