• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.61-70
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• 2004

The operation mode of neural network is divided into learning and recognition process. Learning is updating process of weight until neural network archives target result from input pattern. Recognition is arithmetic process of input pattern and weight. Traditional inner product process is focused to improve processing speed and hardware complexity. There is no hardware architecture to distinguish between loaming and recognition mode of neural network. In this paper we propose the new architecture of low power inner product processor for reconfigurable neural network. The proposed architecture is similar with bit-serial inner product processor on learning mode. It have several advantages which are fast processing base on bit-level, suitability of hardware implementation and pipeline architecture to compute data. And proposed architecture minimizes active units and reduces consumption power on recognition mode. Result of simulation shows that active units is depend on bit representation of weight, but we can reduce active units about 50 precent.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.301-303
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• 2001

In this paper we present a Capacitor Charging Power Supply (CCPS) using a series-resonant three-level inverter topology to improve voltage regulation and use semiconductor switches having low blocking voltage capability such as MOSFETs. This inverter can be operated with two modes, Full Power Mode (FPM) and Half Power Mode (HPM). In FPM inverter supplies the high frequency step up transformer with full DC-link voltage and in HPM with half DC-link voltage. HPM switching method will be adopted when CCPS output voltage reaches the preset target value and operates in refresh mode-charge is maintained on the capacitor. In this topology each semiconductor devices blocks a half of the DC-link voltage[2]. A 15kW, 30kV CCPS has been built and will be tested for an electric precipitator application. The CCPS operates from an input voltage of 500VDC and has a variable output voltage between 10 to 30kV and 1kHz repetition rate at 44nF capacitive load [3]. A resonant frequency of 67.9kHz was selected and a voltage regulation of $0.83\%$ has been achieved through the use of half power mode without using the forced cut off the switch current [1]. The theory of operation, circuit topology and test results are given.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.299-306
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• 2009

Recently, although the power consumption of the flyback converter at the light load and standby power load was minimized by the burst mode operation of PWM IC, flyback converter has still the low efficiency characteristics by the high magnetizing current flowing through magnetizing inductance of transformer. This paper proposes a novel flyback converter with an improved efficiency characteristics and the reduced magnetizing current at the light load and standby power load. Prototype of the 70W multi-output flyback converter for an auxiliary power module of 50 inch PDP TV is built and the experimental results are described.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.86-92
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• 2008

Othogonal Frequency Division Multiplexing(OFDM) has been taken notice of 4th generation communication method because it has a merit of high data rate(HDR). To realize HDR communication, The OFDM a s high efficient Fast-Fourier-Transform (FFT)/Inversion FFT (IFFT) processor. Currently OFDM is realized by Digital Signal Processor(DSP) but it consumes a lot of Power. Therefore, current-mode FFT LSI has been proposed for compensation of this demerit. In this paper, we propose IVC for current-mode FFT LSI. From the simulation result, the output value of IVC is more than 3V when the value of FFT Block output is more than $7.35{\mu}A$. The output value of IVC is lower than 0.5V when the value of FFT Block output is lower than $0.97{\mu}A$. Designed IVC Low-power Current mode FFT LSI will contribute to the operation of current-mode FFT LSI and the development of next generation wireless communication systems.

• Journal of Korea Multimedia Society
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• v.23 no.2
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• pp.293-300
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• 2020

Since the communication networks like the Internet collapses at disaster and calamity sites, a maintenance system that can be operated offline is required for the maintenance of various facilities. In this paper, we propose a system that memory tags attached on the facilities may transmit the emergency manual to a smart-phone, and the smart phone displays it off-line. The main issue is to design low energy mode memory tags. This study presents two kinds of methods and analyzes each's energy consumption mode. The first one is to develop memory tags by using one chip, and the next one is to design memory tags by forming multi-modules. Both ways show proper application fields under the low energy mode. This research selects the off-line maintenance system by using one chip design, and proposes the direction of contents for enhancing the effectiveness of the system. And we expect that this memory tags will be valuable for disaster scenes as well as battle fields.

• Journal of Power Electronics
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• v.18 no.1
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• pp.11-22
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• 2018

This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for renewable energy applications. The proposed converter is composed of a coupled inductor, a passive clamp circuit, a switched capacitor and voltage lift circuits. The passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The configuration of the passive clamp and switched capacitor circuit increases the voltage gain. A wide continuous conduction mode (CCM) operation range, a low turn ratio for the coupled inductor, low voltage stress on the switch, switch turn on under almost zero current switching (ZCS), low voltage stress on the diodes, leakage inductance energy recovery, high efficiency and a high voltage gain without a large duty cycle are the benefits of this converter. The steady state operation of the converter in the continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is discussed and analyzed. A 200W prototype converter with a 28V input and a 380V output voltage is implemented and tested to verify the theoretical analysis.

• Journal of IKEEE
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• v.22 no.3
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Journal of Power Electronics
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• v.18 no.4
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• pp.985-996
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• 2018

The implementation and performance evaluation of an interleaved boundary conduction mode (BCM) boost power factor correction (PFC) converter is presented in this paper by employing three wide band-gap switching devices: a super junction silicon (Si) MOSFET, a silicon carbide (SiC) MOSFET and a gallium nitride (GaN) high electron mobility transistor (HEMT). The practical considerations for adopting wide band-gap switching devices to BCM boost PFC converters are also addressed. These considerations include the gate drive circuit design and the PCB layout technique for the reliable and efficient operation of a GaN HEMT. In this paper it will be shown that the GaN HEMT exhibits the superior switching characteristics and pronounces its merits at high-frequency operations. The efficiency improvement with the GaN HEMT and its application potentials for high power density/low profile BCM boost PFC converters are demonstrated.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.147-148
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• 2011

In this paper, implementation of digital control for critical conduction mode power factor correction (PFC) rectifier is presented. Critical conduction mode is widely used in medium and low power conversion application due to its minimized MOSFET turn-on loss and diode reverse-recovery problem. However, it needs additional zero current detection circuit and maximum frequency limit to properly turn the MOSFET on and avoid the excessive switching loss in light load operation. This paper explains the digital IC implementation and verifies its operation with 200-W prototype PFC rectifier.