• Title/Summary/Keyword: low offset

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An Offset-Compensated LVDS Receiver with Low-Temperature Poly-Si Thin Film Transistor

  • Min, Kyung-Youl;Yoo, Chang-Sik
    • ETRI Journal
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    • v.29 no.1
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    • pp.45-49
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    • 2007
  • The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

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DC-DC Boost Converter using Offset-Controlled Zero Current Sensor for Low Loss Thermoelectric Energy Harvesting Circuit (저 손실 열전변환 하베스팅을 위해 제로전류센서의 오프셋을 조절하는 부스트 컨버터)

  • Joo, Sunghwan;Kim, Kiryong;Jung, Dong-Hoon;Jung, Seong-Ook
    • Journal of IKEEE
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    • v.20 no.4
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    • pp.373-377
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    • 2016
  • This paper presents a low power boost converter using offset controlled Zero Current Sensor (ZCS) control for thermoelectric energy harvesting.[1] [5] Offset controlled ZCS uses adjustable pre-offset that is controled by 6bit code each connected gate of NMOS for switching. Offset controlled ZCS demonstrates an efficiency that is higher than using analog comparator ZCS and that is smaller area than using delay line ZCS. Experimentally, the offset controlled ZCS system consumes 10 times less power than analog comparator ZCS based system at similar performance.

Design and Fabrication of a Offset-PLL with DAC (DAC를 이용한 Offset-PLL 설계 및 제작)

  • Lim, Ju-Hyun;Song, Sung-Chan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.2
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    • pp.258-264
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    • 2011
  • In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

Combined Normalized and Offset Min-Sum Algorithm for Low-Density Parity-Check Codes (LDPC 부호의 복호를 위한 정규화와 오프셋이 조합된 최소-합 알고리즘)

  • Lee, Hee-ran;Yun, In-Woo;Kim, Joon Tae
    • Journal of Broadcast Engineering
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    • v.25 no.1
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    • pp.36-47
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    • 2020
  • The improved belief-propagation-based algorithms, such as normalized min-sum algorithm (NMSA) or offset min-sum algorithm (OMSA), are widely used to decode LDPC(Low-Density Parity-Check) codes because they are less computationally complex and work well even at low SNR(Signal-to-Noise Ratio). However, these algorithms work well only when an appropriate normalization factor or offset value is used. A new method that uses a CMD(Check Node Message Distribution) chart and least-square method, which has been recently proposed, has advantages on computational complexity over other approaches to get optimal coefficients. Furthermore, this method can be used to derive coefficients for each iteration. In this paper, we apply this method and propose an algorithm to derive a combination of normalization factor and offset value for a combined normalized and offset min-sum algorithm to further improve the decoding of LDPC codes. Simulations on the next-generation broadcasting standards, ATSC 3.0 LDPC codes, prove that a combined normalized and offset min-sum algorithm which takes the proposed coefficients as correction coefficients shows the best BER performance among other decoding algorithms.

On the Radial Velocity Offset for [OIII] Emission Line of LINER Galaxies

  • Bae, Hyun-Jin;Woo, Jong-Hak;Yagi, Masafumi;Yoon, Suk-Jin;Yoshida, Michitoshi
    • The Bulletin of The Korean Astronomical Society
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    • v.37 no.1
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    • pp.33.2-33.2
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    • 2012
  • Low-ionization nuclear emission-line region (LINER) galaxies constitute a major fraction of low-luminosity AGN population in the local Universe. In contrast to Seyfert galaxies, it is theoretically expected that LINERs would not have an outflow due to their low Eddington ratio. Using Keck/LRIS spectroscopy on a nearby LINER galaxy SDSS J091628.05+420818.7, we find a significant radial velocity offset for [OIII]${\lambda}$5007 emission line as - 50 km $s^{-1}$ blueshifted compared to systemic velocity of the galaxy, while other emission lines exhibit no or little offset. The observed [OIII] velocity offset possibly indicates an outflow of gas in the LINER galaxy, and it is probable that we only detected the [OIII] velocity offset because [OIII] ionization region is closer to the accretion disk, hence, more affected by an outflow. We further investigate the [OIII] velocity offset of -4000 SDSS AGN-host galaxies to compare the strength of AGN outflow. We find that a number of both LINER and Seyfert galaxies show [OIII] velocity offset, but the fraction of LINER galaxies with velocity offset is smaller than that of Seyfert galaxies. The preliminary results imply the presence of gas outflow in LINER galaxies, although outflow strength is probably weaker compared to Seyfert galaxies.

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Low-Power Frequency Offset Synchronization Block Design and Implementation using Pipeline CORDIC (Pipeline CORDIC을 이용한 저전력 주파수 옵셋 동기화기 설계 및 구현)

  • Ha, Jun-Hyung;Jung, Yo-Sung;Cho, Yong-Hoon;Jang, Young-Beom
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.10
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    • pp.49-56
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    • 2010
  • In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

Effects of Lap Splice Details on Seismic Performance of RC Columns (RC기둥의 내진성능에 미치는 겹침 이음상세의 영향)

  • Kim, Chul-Goo;Park, Hong-Gun;Kim, Tae-Wan;Eom, Tae-Sung
    • Journal of the Earthquake Engineering Society of Korea
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    • v.20 no.6
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    • pp.351-360
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    • 2016
  • In regions of low-to-moderate seismicity, various types of lap splices are used for longitudinal reinforcement of columns at the plastic hinge zones. The seismic performance of such lap spliced columns, such as strength, deformation capacity, and energy dissipation, is affected by material strengths, longitudinal re-bar size, confinement of hoops, lap splice location, and lap splice length. In the present study, cyclic loading tests were performed for columns using three types of lap splices (bottom offset bar splice, top offset bar splice, and splice without offset bend). Lap splice length($40d_b$ and $50d_b$) was also considered as test parameters. Ties with 90-degree end hooks were provided in the lap splice length. The test results showed that strength, deformation capacity, and energy dissipation of columns significantly differed depending on the details and the length of lap splices. The bottom offset bar splice showed high ductility and energy dissipation but low strength; on the other hand, the top offset bar splice and the splice without offset bend showed high strength but moderate ductility and energy dissipation.

Multi-time Programmable standard CMOS ROM memory cell (여러 번 프로그래밍이 가능한 표준 CMOS 공정의 MTP (Multi-times Programmable) ROM 셀)

  • Chung, In-Young
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.455-456
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    • 2008
  • New CMOS ROM cell is reported in this paper, distinguished from conventional ones in that it can be re-programmed by multi-times. It uses the comparator offset as the physical storage quantity and the MOSFET FN stress effect for offset programming. It demands very low offset for read, and works well in very low voltage. It can become a promising ROM solution for various SoC systems.

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A Low Complexity Frequency Offset Estimation Scheme for OFDM Systems (OFDM 시스템에 알맞은 낮은 복잡도의 주파수 옵셋 추정 기법)

  • Lee, Young-Yoon;Chong, Da-Hae;Yoon, Tae-Ung;Song, Chong-Han;Kim, Sang-Hun;Park, So-Ryoung;Yoon, Seok-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.5C
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    • pp.548-554
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    • 2009
  • OFDM systems are very sensitive to the frequency offset. Therefore, frequency offset estimation is one of the most important procedures in OFDM systems. Ren's periodogram-based frequency offset estimation scheme consists of three steps which estimates the frequency offset accurately. However, there are the drawbacks of the limited frequency offset estimation ranges in the second and third estimation steps of the Ren's scheme. This ranges are insufficient compared with the overall signal bandwidth, making the high complexity of the first estimation step. In this paper, we propose a novel lower complexity frequency offset estimation scheme for OFDM systems which extends the frequency offset estimation range. The simulation results show that the proposed scheme has a wider frequency offset estimation range and lower complexity than those of the Ren's scheme.

Eliminating Method of Estimated Magnetic Flux Offset in Flux based Sensorless Control of PM Synchronous Motor using High Pass filter with Variable Cutoff Frequency (모터 운전 주파수에 동기화된 차단주파수를 갖는 HPF(High pass filter)를 적용한 영구자석 동기전동기의 자속기반 센서리스 제어의 추정 자속 DC offset 제거 기법)

  • Kang, Ji-Hun;Cho, Kwan-Yuhl;Kim, Hag-Wone
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.20 no.3
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    • pp.455-464
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    • 2019
  • The sensorless control based on the flux linkage of PM synchronous motors has excellent position estimation characteristics at low speeds. However, a limitation arises because the integrator of flux estimator is saturated by the DC offset generated during the analog to digital conversion(ADC) process of the measured current. In order to overcome this limitation, HPF with a low cutoff frequency is used. However, the estimation performance is deteriorated (Ed- the verb deteriorate already includes the meaning of 'problem') at high speed due to the low cutoff frequency, and increasing the cutoff frequency of the HPF induces further problems of phase leading and initial starting failure at low speeds. In this paper, the cutoff frequency of HPF was synchronized to the operation frequency of the motor: at low speeds the cutoff frequency was set to low in order to reduce the phase leading of the estimated flux, and at high speeds it was set to high to raise the DC offset removal performance. As a result, the operating range was increased by 200%. Furthermore, a phase compensation algorithm is proposed to reduce the phase leading of the HPF to less than 1.5 degrees over the full operating range. The proposed sensorless control algorithm was verified by experiment with a PM synchronous motor for a washing machine.