• 전자공학회논문지T
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• 제35T권1호
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• pp.29-32
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• 1998

실리콘 산화막에서 저레벨 누설전류를 조사하였다. 저레벨 누설전류는 전이요소와 직류요소로 구성되어 있다. 전이요소는 스트레스에 의해 두 계면트랩 가까이 발생된 트랩의 충방전에 의한 터널링으로 나타났으며 직류요소는 산화막을 통한 트랩 어시스트 터널링으로 나타났다 그리고 저레벨 누설전류는 산화막에서 발생된 트랩의 수에 비례하였다. 저레벨 누설전류는 트랩의 충방전 누설전류이며 비휘발성 소자의 데이터 유지능력에 영향을 주었다.

• 전기학회논문지
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• 제56권5호
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• pp.938-943
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• 2007

In this paper, we show that, in case of piezoelectric micropower generator, just replacing Schottky diodes in the bridge rectifier with ultra-low reverse leakage current diodes improves the mechanical-to-electrical energy conversion efficiency by more than 100%. Experimental and PSPICE simulation results show that, due to the ultra-low leakage current, the charging speed of the circuit employing PAD1 is higher than that of the circuit employing Schottky diodes and the saturation voltage of the circuit employing PAD1 is also higher. This study suggests that , when the internal impedance of source is very large (a few tens of $M{\Omega}$) such that maximum charging current is a few microamperes or less, in order to realize literally the energy scavenging system, ultra-low reverse leakage current diodes should be used for efficient energy conversion. Since low-level vibration is ubiquitous in the environment ranging from human movement to large infrastructures and the mechanical-to-electrical energy conversion efficiency is much more critical for use of these vibrations, we believe that the improvement in the efficiency using ultra-low leakage diodes, as found in this work, will widen greatly the application of piezoelectric micropower generator.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.36-41
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• 2003

This paper presents the results of power spectra using the fundamental and low frequency harmonic components of leakage current waveform to study aging on contaminated EPDM insulator(was serviced during 1997-2001, region Pohang, korea) under salt fog conditions. Experiments have been conducted in the chamber salt fog and at the 16KVrms. The salt contents adjusted as 0g,25g,50g and 75g per liter of deionized water. The onset of dry-band arcing on polymer insulators could be determined by signal processing the low frequency harmonics components. A correlation has been found between the fundamental and low harmonic components of power spectra on leakage current. Where aging could be associated with an increase in the level of both the fundamental and low frequency harmonics components of leakage current. Surface aging for contaminated EPDM insulators occurred when the fundamental component of leakage current was greater then some level On the other hand, when the polymer insulator approached failure, the fundamental component of leakage current reached relatively high values and low frequency harmonics components of the leakage current trended to decrease. The results suggest that both the fundamental and low frequency harmonics of leakage current can be used as a tool to determine both the beginning of aging and before flashover, end of life EPBM insulator in salt fog.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• ETRI Journal
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• 제31권6호
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• pp.725-731
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• 2009

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate-triggered NMOS and a gate-substrate-triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn-on speed. The proposed ESD protection devices are designed using 0.13 ${\mu}m$ CMOS technology. The experimental results show that the proposed substrate-triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn-on time of 37 ns. The proposed gate-substrate-triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.

• Restorative Dentistry and Endodontics
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• 제25권1호
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• pp.85-90
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• 2000

For more esthetic treatments the use of composite in molar areas are increasing. But polymerzation shrinkage that cause marginal leakage and cuspal deflection has been the problems of composites. The purpose of this study is to compare the effect of low intensity curing and polishing period on marginal leakage. Cavities were prepared on the buccal or lingual surface of forty five sound extracted human teeth and etching, application of bonding agent and filling of composite was done. Group 1 was light cured at intensity of 600$mW/cm^2$ for 41 seconds and polished. Group 2 was light cured at intensity of 300$mW/cm^2$ for 2 seconds and polished and after polishing it was light cured for 40 seconds at 600$mW/cm^2$. Group 3 was light cured at intensity of 300$mW/cm^2$ for 2 seconds and waited for 5 minutes and after curing at 600$mW/cm^2$ for 40 seconds polishing was done. The specimens were thermocycled at $5^{\circ}C$ and $55^{\circ}C$ for 1000 cycles and immersed in 2% methylene blue solution for 24 hours. Composite-tooth interface was examined under stereobinocular microscope for dye penetration. The results were as follows : 1. Group which were cured at low intensity and polished after curing at high intensity showed less marginal leakage than group which were cured at high intensity for 41 seconds(p<0.05). 2. Marginal leakage between group which were cured at low intensity and polished immediately and group which were cured at high intensity for 41 second were not significantly different. Light curing at low intensity can reduce marginal leakage but polishing immediately after curing at low intensity for short time can affect marginal leakage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1705-1708
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• 2006

Nanocrystalline silicon (nc-Si) based TFTs were developed using a conventional PECVD production system. Devices exhibit very interesting characteristics, in particular when using a bi-layer structure which reduces leakage current and improves subthreshold area. Good stability and low leakage current make these devices suitable for the fabrication of low-cost and high performance AMOLED displays.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1069-1071
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• 1995

The electrical properties of Al/TiN/Ti contact are investigated at submicron contacts. The contact resistance and contact leakage current are dependent on metallization, surface dopant concentration, semiconductor surface treatment and contact plug ion implantation. In this paper, the contact resistance and contact leakage current are studied according to surface dopant concentration, semiconductor surface treatment and contact plug ion implantation at 0.8 micron contact. The contact resistance and contact leakage current increases with increasing substrate ion concentration. HF cleaning represents high contact resistance but low contact leakage current while CDE cleaning represents low contact resistance but high contact leakage current. Contact plug ion implantation decreases contact resistance but increases contact leakage current. Specially, RTA represents good electrical properties.