• 제목/요약/키워드: low jitter

검색결과 157건 처리시간 0.022초

인터넷전화에서 지터보상을 위한 Frame Extension for Adaptive Playout Time(FEAPT) 알고리즘 (FEAPT Algorithm to compensate Jitter in Internet Phone)

  • 남재현
    • 한국정보통신학회논문지
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    • 제7권6호
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    • pp.1168-1176
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    • 2003
  • 인터넷 전화 서비스는 저렴한 가격과 타 서비스와 통합 및 가치부가면에서 기존의 전화에 비해 많은 장점을 가지고 있으나, 상대적으로 낮은 음질로 인하여 사용자의 요구를 만족시키지 못하고 있다. 이것은 인터넷이 best-effort형 패킷 전달 서비스만을 제공하고 있기 때문에 지연, 패킷 손실 및 지터 등을 보장할 수 없기 때문이다. 본 논문에서는 인터넷 전화에서 전송지연으로 인한 패킷손실을 감소시키기 위해 수신 패킷을 사람이 인지 가능한 수준까지 확장하여 playout 시킬 수 있는 FEAPT 알고리즘을 제시한다.

Adaptive Temporal Rate Control of Video Objects for Scalable Transmission

  • Chang, Hee-Dong;Lim, Young-Kwon;Lee, Myoung-Ho;Ahan, Chieteuk
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 1997년도 Proceedings International Workshop on New Video Media Technology
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    • pp.43-48
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    • 1997
  • The video transmission for real-time viewing over the Internet is a core operation for the multimedia services. However, its realization is very difficult because the Internet has two major problems, namely, very narrow endpoint-bandwidth and the network jitter. We already proposed a scalable video transmission method in [8] which used MPEG-4 video VM(Verification Model) 2.0[3] for very low bit rate coding and an adaptive temporal rate control of video objects to overcome the network jitter problem. In this paper, we present the improved adaptive temporal rate control scheme for the scalable transmission. Experimental results for three test video sequences show that the adaptive temporal rate control can transfer the video bitstream at source frame rate under variable network condition.

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Chip Timing Recovery Algorithm Robust to Frequency Offset and Time Variant Fading

  • Kang, Hyung-Wook;Lee, Young-Yong;Park, Hyung-Jin
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -3
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    • pp.1948-1951
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    • 2002
  • In this paper, we propose a chip timing recovery algorithm that is robust to frequency offset and time variant fading environments for DS/CDMA. The proposed structure is a modified non-coherent Delay Locked Loop (DLL) that employs a decimator. Analytical expression for the proposed non-coherent DLL S-curve and steady-state timing jitter is derived and confirmed by computer simulation. The results show that the proposed structure can reduce a steady-state timing jitter of the regenerated spreading code replica to frequency offset and time-variant fading in mobile radio channel, especially in very low SNR.

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Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

  • Na, Seung-in;Kim, Susie;Yang, Youngtae;Kim, Suhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권3호
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    • pp.319-329
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    • 2016
  • High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

유지 기능을 가지는 위상고정 루프를 이용한 40 Gb/s 클락 복원 모듈 설계 및 구현 (Design and Implementation of 40 Gb/s Clock Recovery Module Using a Phase-Locked Loop with hold function)

  • 박현;우동식;김진중;임상규;김강욱
    • 한국전자파학회:학술대회논문집
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    • 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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    • pp.191-196
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    • 2005
  • A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

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가상 현실 어플리케이션을 위한 관성과 시각기반 하이브리드 트래킹 (Hybrid Inertial and Vision-Based Tracking for VR applications)

  • 구재필;안상철;김형곤;김익재;구열회
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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    • pp.103-106
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    • 2003
  • In this paper, we present a hybrid inertial and vision-based tracking system for VR applications. One of the most important aspects of VR (Virtual Reality) is providing a correspondence between the physical and virtual world. As a result, accurate and real-time tracking of an object's position and orientation is a prerequisite for many applications in the Virtual Environments. Pure vision-based tracking has low jitter and high accuracy but cannot guarantee real-time pose recovery under all circumstances. Pure inertial tracking has high update rates and full 6DOF recovery but lacks long-term stability due to sensor noise. In order to overcome the individual drawbacks and to build better tracking system, we introduce the fusion of vision-based and inertial tracking. Sensor fusion makes the proposal tracking system robust, fast, accurate, and low jitter and noise. Hybrid tracking is implemented with Kalman Filter that operates in a predictor-corrector manner. Combining bluetooth serial communication module gives the system a full mobility and makes the system affordable, lightweight energy-efficient. and practical. Full 6DOF recovery and the full mobility of proposal system enable the user to interact with mobile device like PDA and provide the user with natural interface.

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변성발성장애 환자에 대한 음성치료의 효과 (The Efficiency of Voice Therapy for the Patients with Mutational Falsetto)

  • 표화영
    • 대한후두음성언어의학회지
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    • 제9권2호
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    • pp.134-141
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    • 1998
  • Mutational falsetto is a kind of voice disorders due to the failure to acquire proper low-pitched voice during the puberty. The patients with mutational falsetto can produce the normal low-pitched voice by the surgical treatment, like the type III-thyroplasty, or the voice therapy. The present study is, focusing on the latter treatment, to consider the efficiency of voice therapy for the mutational falsetto. The 7 patients who were diagnosed as mutational falsetto by the laryngologists, and treated by the voice therapist were selected as subjects. Their voices of pretherapy and posttherapy were analyzed on the aspects of acoustics and aerodynamics. Acoustic analysis was done by the MDVP(Multidimensional Voice Program) of CSL(Computerized Speech Lab, Kay Elemetrics, Co.), and aerodynamic analysis, by the Maximum Sustained Phonation of Aerophone II(Kay Elemetrics, Co.). By these measurements, we could find that fundamental frequency(F0) was significantly lowered, on the average, 65Hz. Maximum phonation time(MPT) was increased 4.57 second, and shimmer was decreased 1.644%, respectively, and each changes was statistically significant, too. On the average, jitter was decreased 0.499%, mean flow rate(MFR) was decreased 27.71ml/sec, and NHR was increased 0.023 which was the only parameter not showing improvement. But the changes of jitter, MFR and NHR were not statistically significant.

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지그시스템을 이용한 VCXO의 스펙트럼 분석 및 성능평가 (Spectral Analysis and Performance Evaluation of VCXO using the Jig System)

  • 윤달환
    • 전자공학회논문지SC
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    • 제43권4호
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    • pp.45-52
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    • 2006
  • 본 연구에서는 위상잡음과 지터(jitter) 특성을 개선한 $5mm{\times}7mm$ 크기의 적층 세라믹 SMD(surface mounted device)형 VCXO를 개발한다. PECL(positive emitter coupled logic) 칩패키지를 발진수정자에 결선한 VCXO는 그 길이 및 패키지 내부의 패턴 등에 의하여 부유인덕턴스 및 기생 커패시턴스가 발생하고, 전원의 반사 및 잡음 발생으로 출력신호의 진폭 감소 및 신호 손실이 발생하여 발진기 성능을 정상적으로 평가할 수 없다. 이러한 신호 손실 및 진폭감소를 방지하기 위해 지그(Jig) 시스템을 개발하고, 이를 통하여 발진기의 정확한 스펙트럼 분석 및 성능을 평가한다. 동작전원은 3.3 V, 주파수 범위 120-180 MHz 및 Q인수는 5K이다.

A 1.25 GHz Low Power Multi-phase PLL Using Phase Interpolation between Two Complementary Clocks

  • Jin, Xuefan;Bae, Jun-Han;Chun, Jung-Hoon;Kim, Jintae;Kwon, Kee-Won
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권6호
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    • pp.594-600
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    • 2015
  • A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

PECL과 역메사형 HFF를 이용한 소형세라믹 VCXO 개발 (Development of a Small Size Ceramic VCXO using the PECL and Inverted Mesa Type HFF)

  • 윤달환;이재경
    • 전자공학회논문지SC
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    • 제42권1호
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    • pp.23-31
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    • 2005
  • 통신시스템의 경박단소화와 고부가가치 기술 추세에 따라 전압제어 수정발진기(VCXO)도 소형화와 경향화를 향하고 있다. 기존의 VCXO는 9×14mm의 크기가 주류를 이루었으나 양의 에미터결합논리(PECL)와 적층 세라믹 SMD 패키지기술을 통하여 5×7 mm의 크기로 소형화한 VCXO를 개발한다. 이는 역메사형 HFF 수정설계 기술과 세라믹 SMD 공정선을 접목시키고 생산프로세스를 단축하는 효과도 얻는다.