• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• 전자공학회논문지
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• 제50권12호
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• pp.33-39
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• 2013

지연고정루프는 위상고정루프에 비해 작은 지터 값을 가지고 있음에도 불구하고 지연고정루프를 사용해서 지터를 줄이려는 연구는 꾸준히 이루어지고 있다. 이러한 연구의 결과로 기본 구조를 변형하거나 또는 다양한 구조들을 첨가하여 지터 특성을 개선하였다. 이 논문에서는 지연고정루프에서 다양한 루프필터 구조를 적용하면 지터 특성이 향상될 수 있음을 보여준다. 다양한 루프필터가 적용된 지연고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계 하였다.

• 한국통신학회논문지
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• 제15권5호
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• pp.353-363
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• 1990

본 논문은 Data Bit Jitter(DBJ)가 Data 동기수신회로의 Bit Slip Rate(BSR) 에 미치는 영향에 관하여 고찰하였다. 특히 이 논문에서는 BSR치를 계산하는데 필요한 특성 jitter parameter 들을 부각시켰으며 또한 DBJ에 관한 새로운 규격설정을 제시하였다. 새로이 제시된 방법에 의하면 종래의 방법에 비하여 복잡해진 점은 있으나, 반면 보다 현실적이고 보다 더 정확하게 DBJ의 BSR에 관한 영향을 예측할 수 있는 장점이 있다고 생각된다. 새로이 제시된 방법에서는 수신기에 의존하는 parameter들이 부각되었으며 jitter spectrum의 각 부분(저주파, 고주파 부분등)에 대한 적절한 비중이 고려되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of the Optical Society of Korea
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• 제13권3호
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• pp.373-378
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• 2009

An Ethernet passive optical network (EPON) is a low-cost, high-speed solution to the bottleneck problem of a broadband access network. This paper analyzes the delay and the jitter performance of dynamic bandwidth allocation (DBA) schemes for differentiated services in EPONs. Especially, the average packet delay and the delay jitter of the expedited forwarding (EF) traffic class are compared, with consideration as to whether a cyclic or an interleaved polling scheme is superior. This performance evaluation reveals that the cyclic polling based DBA scheme provides constant and predictable average packet delay and improved jitter performance for the EF traffic class without the influence of load variations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1630-1633
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• 2002

In this paper, we proposed a new control system of the dividing ratio changeable type ADPLL (DCPLL). The DCPLL has been designed by us. However, in the DCPLL, there are some problems such as this curcuit is increased the output jitter on multiple frequency, and the output jitter is large on steady state. Then, the output jitter characteristic on multiple frequency is improved by using “rest-control” system. Also, output jitter decreases by using “W-edge (positive edge h negative edge)” system. We confirmed some characteristics of the DCPLL with the circuit simulator, PSpice.

• 한국음향학회지
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• 제42권4호
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• pp.298-303
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• 2023

본 연구는 장애음성의 평가에 사용되는 연속발화과제로서 유성음 문장의 임상적 유용성을 알아보기 위한 것이다. 이를 위해, 모음연장발성과제의 음향학적 측정치인 주파수 변동률(jitter percent, jitter), 진폭 변동률(shimmer percent, shimmer), 소음대배음비(Noise to Harmonic Ratio, NHR)와 유성음으로만 이루어진 연속발화과제의 음향학적 측정치로 캡스트럼 분석 측정치인 켑스트럼 피크 현저성(Cepstral Peak Prominence, CPP), 저주파수대고주파수 스펙트럼비(Low/High spectral ratio, L/H ratio)의 상관을 분석하였다. 음성장애 환자 65명을 대상으로 수집된 자료를 분석한 결과, 유성음 문장의 음향학적 측정치인 CPP와 모음연장발성의 측정치인 jitter(r = -.624, p = .000), shimmer (r = -.530, p = .000), NHR(r = -.469, p = .000) 간에 유의한 상관이 나타났다. 이는 유성음 문장의 캡스트럼 측정치가 '연속발화 과제의 변동률 기반 분석 불가능', '분석구간과 길이에 따른 결과차이' 등 언어재활 임상현장이 가지고 있는 장애음성의 음향학적 분석의 제한에 대한 대안으로 유용하게 사용될 수 있음을 시사한다.

• 한국광학회:학술대회논문집
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• 한국광학회 2000년도 제11회 정기총회 및 00년 동계학술발표회 논문집
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• pp.276.2-278
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• 2000

In a recent years, a number of approaches have been studied, including passive, active, and hybrid mode-locking of semi-conductor lasers for short pulse generation and research has been devoted to achieve low timing-jitter operation since the timing jitter is unfavorable for system applications. Among the methods of mode locking, passive mode locking does not need external rf drives, and therefore the operation and fabrication procedures are simplified. In spite of these attractive advantages of passive mode-locked laser, it has critical drawbacks such as large timing jitter and the difficulty in synchronization with external circuits. Their inherent large timing jitter value was shown to be suppressed to certain levels by means of hybrid mode-locking technique$^{(1)}$ , where the saturable absorber section was modulated by an external signal with the cavity round trip frequency. Furthermore, the subharmonic mode-locking (SHML) technique alleviates the restrictions of high speed driving electronics. It has been demonstrated experimentally$^{(1)}$ that the hybrid subharmonic mode-locking technique has lead to significant reduction of the timing jitter. (omitted)