A Low Jitter on Multiple Frequency of Dividing Ratio Changeable Type ADPLL

In this paper, we proposed a new control system of the dividing ratio changeable type ADPLL (DCPLL). The DCPLL has been designed by us. However, in the DCPLL, there are some problems such as this curcuit is increased the output jitter on multiple frequency, and the output jitter is large on steady state. Then, the output jitter characteristic on multiple frequency is improved by using “rest-control” system. Also, output jitter decreases by using “W-edge (positive edge h negative edge)” system. We confirmed some characteristics of the DCPLL with the circuit simulator, PSpice.