• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• 전자공학회논문지A
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• 제30A권2호
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.109-111
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• 2002

We have demonstrated all-opticalflip-flop based on optical bistability in a SOA/DFB-SOA with broadband gain. Input signal with the wavelength of 1340.23 nm or 1680.93 nm and the current of about 98% of the lasing threshold is injected into theDFB-SOA. Current injected into SOA is 80 mA All-optical flip-flop has various applications such as all-optical memory, demultiplexing, packet-header buffering, and retiming.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• 제어로봇시스템학회논문지
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• 제5권7호
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• pp.848-854
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• 1999

In this paper, we designed and implemented a precise pulse motor controller chip that generates the pulse needed to control step motor, DC servo and AC servo motors. This chip generates maximum pulse output rate of 5Mpps and has the quasi-S driving capability and speed and moving distance override capability during driving. We designed this chip with VHDL and executed a logic simulation and synthesis using Synopsys tool. The pre-layout simulation and post-layout simulation was executed by Compass tool. This chip was produced with 100 pins, PQFP package by 0.8${\mu}{\textrm}{m}$ gate array process and implemented by completely digital logic. We developed the test hardware board of performance and the CAMC(Computer Aided Motor Controller) Agent softwate to test the performance of the pulse motor controller chip produced. CAMC Agent enables user to set parameters needed to control motor with easy GUI(Graphic User Interface) environment and to display the output response of motor graphically.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• 한국통신학회논문지
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• 제12권3호
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• pp.292-297
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• 1987

선진국에서 硏究 開發하고 있는 各種 高速 GaAs 集積論理 gate 回路의 調査, SPICE 分析 硏究結果 動作特性 回路集積度 有用性 動作條件 製造技術의 制限 및 應用等에 대한 比較値를 얻었다. 우리나라에서 政策硏究課題로 되어 있는 高速 GaAs IC's 硏究開發에 본 論文이 참고가 될 것으로 사료된다.

• 한국군사과학기술학회지
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• 제5권2호
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권9호
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• pp.546-551
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• 2000

A micromechanical switch that can be used as a logic gate is described in this paper. This switch consists of fixed input electrodes an output electrode Vcc/GND electrodes and movable plates suspended by crab-leg flexures. for mechanical switching of an electrical signal a parallel plate actuator which comes in contact with output electrode was used. Provided that movable plates are connected to Vcc and a low input voltage(ground signal) is applied to the fixed input electrodes the movable plates are pulled by an electrostatic force between the fixed input electrodes and the movable plates. the proposed micromechanical switch was fabricated by surface micromachining technology with$2\mum$ -thick poly-Si and the measured threshold voltage for ON/OFF switching was 23.5V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.111-114
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• 2000

Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.