• Journal of Information Processing Systems
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• v.7 no.1
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• pp.85-92
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• 2011

This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays ("mesh", for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size $m{\times}m$ with static row/column buses to simulate the mesh of the larger size $n{\times}n$ with reconfigurable row/column buses ($m{\leq}n$). This means that if a problem can be solved in O(T) time by the mesh of size $n{\times}n$ with reconfigurable buses, then the same problem can be solved in O(Tn/m (n/m + log m)) time on the mesh of a smaller size $m{\times}m$ without a reconfigurable function. This time-cost is optimal when the relation $n{\geq}m$ log m holds (e.g., m = $n^{1-\varepsilon}$ for $\varepsilon$ > 0).

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.19-24
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• 2011

As era of multi-core processors has arrived, transactional memory has been considered as an effective method to achieve easy and fast multi-threaded programming. Various hardware transactional memory systems such as UTM, VTM, FastTM, LogTM, and LogTM-SE, have been introduced in order to implement high-performance multi-core processors. Especially, LogTM-SE has provided study performance with an efficient memory management policy and a practical thread scheduling method through conflict detection based on signatures. However, increasing number of cores on a processor imposes the hardware complexity for signature processing. This causes overall performance degradation due to the heavy workload on signature comparison. In this paper, we propose a new architecture of multiple signature comparison to improve conflict detection of signature based transactional memory systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.847-854
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• 2001

The Web continues to grow fast rate in both a large aclae volume of traffic and the size and complexity of Web sites. Along with growth, the complexity of tasks such as Web site design Web server design and of navigating simply through a Web site have increased. An important input to these design tasks is the analysis of how a web site is being used. The is paper proposes a Page logging System(PLS) identifying reliably user sessions required in Web mining system PLS consists of Page Logger acquiring all the page accesses of the user Log processor producing user session from these data, and statements to incorporate a call to page logger applet. Proposed PLS abbreviates several preprocessing tasks which spends a log of time and efforts that must be performed in Web mining systems. In particular, it simplifies the complexity of transaction identification phase through acquiring directly the amount of time a user stays on a page. Also PLS solves local cache hits and proxy IPs that create problems with identifying user sessions from Web sever log.

• Journal of Information Processing Systems
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• v.7 no.4
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• pp.613-626
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• 2011

In this paper, we focus on the pinwheel task model with a variable voltage processor with d discrete voltage/speed levels. We propose an intra-task DVS algorithm, which constructs a minimum energy schedule for k tasks in O(d+k log k) time We also give an inter-task DVS algorithm with O(d+n log n) time, where n denotes the number of jobs. Previous approaches solve this problem by generating a canonical schedule beforehand and adjusting the tasks' speed in O(dn log n) or O($n^3$) time. However, the length of a canonical schedule depends on the hyper period of those task periods and is of exponential length in general. In our approach, the tasks with arbitrary periods are first transformed into harmonic periods and then profile their key features. Afterward, an optimal discrete voltage schedule can be computed directly from those features.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2690-2700
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• 1997

This paper presents parallel sorting algorithm, SHARED-MEMORY-BS and REDUCED-BS, which are implemented on shared-memory parallel computers. These algorithm sort N keys in $O(log^2N)$ time. REDUCED-BS users a parity strategy which gives an idea for the efficient usage of the local memory associated with each processor. By taking advantage of the local memory associated with each processor, the communication of REDUCED-BS is decreased by approximately half that of SHARED-MEMORY-BS. On the basis of alleviating the communication, the algorithm REDUCED-BS results in a significant improvement of performance.

• Journal of KIISE
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• v.42 no.4
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• pp.442-450
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• 2015

This paper proposes a method for reducing false conflicts in signature-based eager hardware transactional memory (HTM). The method tracks the information on all cache blocks that are accessed by a transaction. If the information provides evidence that there are no conflicts for a given transactional request from another core, the method prevents the occurrence of a false conflict by forcing the HTM to ignore the decision based on the signature. The method is very effective in reducing false conflicts and the associated unnecessary transaction stalls and aborts, and can be used to improve the performance of the multicore processor that implements the signature-based eager HTM. When running the STAMP benchmark on a 16-core processor that implements the LogTM-SE, the increased speed (decrease in execution time) achieved with the use of the method is 20.6% on average.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.554-560
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• 1995

In this paper, we suggest a parallel algorithm to merge priority queues organized in two heaps, kheap and nheap of sizes k and n, correspondingly. Employing max(2$^{-1}$, $\ulcorner$(m＋1)/4$\lrcorner$'s processors, this algorithm requires O(log(n/k)＊log(n)) on an EREW-PRAM, where i is the height of the heap and m is the summation of sizes n and k. Also, when we run it on the MasPar machine, this method achieves a 33.934-fold speedup with 64 processors to merge 8 million data items which consist of two heaps of different sizes. So our parallel algorithm's EPU is close to 1, which is considered as an optimal speedup ratio.eedup ratio.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.