• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Korean Journal of Optics and Photonics
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• v.21 no.2
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• pp.74-81
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• 2010

A modeling methodology for the analysis of injection-locked Fabry-Perot laser diodes (FP-LDs), promising for cost-effective WDM-PON sources, is proposed. The time-domain large-signal model that is used is found to provide quite similar results to some experimental ones. With our methodology, we model characteristics of FP-LDs, such as influence of reflectivity at a facet and detuning on injection-locking. The eye diagram characteristics are also investigated. It is observed that the facet reflectivity at the injection side should be lower than 1% to provide stable operation in terms of good side-mode suppression ratio and independence from detuning between narrow-band injection noise and LD modes. It is also observed that good eye opening can be obtained for 155 Mbps modulation while the parameters such as the active region thickness should be properly optimized to obtain reasonable eye opening at 1.25 Gbps.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.526-533
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• 2006

In this paper, we presented the synchronization module between RF shower system and RFID Reader to extend interrogating range on Mobile RFID system, Costas Loop and FPLL(Frequency/phase Lock Loop) were used. We achieved compromised range of 3MHz locking frequency, 1ms locking time and figured out remarkable Hopping frequency of the Reader. The prototype of the new designed RFID system has been tested with ISO18000-6 type-B Tag. The read range between designed RFID Reader and Tag has been measured, it increased triple times by adjusting the Shower system output level.

• Journal of the Korea Furniture Society
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• v.27 no.2
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• pp.104-110
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• 2016

The aim of this study is to develop and suggest the handle for lockers according to the design process which are used for keeping of student's personal stuffs such as books, writing implements and gym uniform in elementary, middle and high school and university as well. This includes the design development for ILGUMTUR which is specialized for office furniture, but does not own the intellectual property right yet. The design concept based on the domestic locker market survey is recessed handle at low- to intermediate price and it's material should be plastic what is solid and light. The lock system should be constructed by molding process and the name plate can be exchanged every time the owner of locker changes. Contrary to the right angle of it's external appearance, the handle of the locker is designed to be softly round and the simplicity is pursued for an easy production. On the basis of this design concept the sketch has been drawn and upgraded in full by 3D-rendering. Then the mock-up has been completed by 3D printer and ILGUMTUR has obtained a patent for the locking system based on the rotation of 2 circles.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.295-296
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• 2006

We developed wire frame drive unit based on SMA for the 3D Shape display. Our basic concept is wire frame combination connected with a chain form which can create various shapes and it compared with pin array mechanism which is not able to display mushroom shape. It imitates antagonist mechanism of human musculoskeletal system. we create similar motion using repair-relaxation mechanism and locking mechanism by SMA. Therefore, in this paper, we propose SMA control solution for actuating repair-relaxation mechanism and locking mechanism. In our control system. we use optical sensor and quantitative angle between wire frames for closed loop control. And we supply amplified current for SMA by circuit composed of transistor and apply PWM signal to circuit for efficient control. So, wire frame drive unit enable diversity angle control based on sensor data. And then combination of wire frame drive units will create various objects.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• The Journal of Korea Robotics Society
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• v.17 no.2
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• pp.238-244
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• 2022

Maintenance works of offshore wind turbines could take a longer time, which causes the reduction of their energy production efficiency, than those of onshore wind turbines owing to severe offshore environment. Subsequently, preventive maintenance measures are required to increase the production efficiency. Thus, we proposed a wheel-based Underwater Pole Climbing Robot (UPCR) platform, which was aimed at the periodic inspection and maintenance of the substructures of the offshore wind turbines, with three advantages: high speed, good mobility and low power consumption. In the proposed platform, a self-locking system using a gripper module was adopted for preventing slippery problem and a dual configuration was chosen for moving on a branched structure. As a result, the proposed robot was able to continuously climb, preserve it's position at the pole without consuming energy, and move from the pole to the other branched pole. The results of this research show that the UPCR has basic moving capabilities required for the underwater work for the substructures of the offshore wind turbines.

• Journal of the military operations research society of Korea
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• v.17 no.2
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• pp.90-99
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• 1991

In this paper a dispatching rule, $D^{*}$, for AGV operations in automated manufacturing system is proposed to improve the performance measures. And the algorithm is compared with existing heuristic rules via simulation to evaluate its capabilities. It is shown that the proposed rule enhances mean flow time, makespan and throughput, and avoids the locking phenominon which can be fatal to the operation of automated manufacturing systems.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1201-1204
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• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.