• Journal of the Korean Society for Library and Information Science
• /
• v.17
• /
• pp.11-47
• /
• 1989

This study intends to examine the background and the procedure of the carving of the tablets of the second edition of Dae-Jang-Mock­Lock(재조대장목록). the time and the route of the moving of the tablets. into Haein-sa, and the contents and the system of it. This study is mainly based on the second edition of Dae-Jang-Mock-Lock. But the other closely related materials such as restored first. edition of the Dae- Jang-Mock-Lock, Koryo Sin-Jo-Dae-Jang-Byeol-Lock (고려신조대장교정별록). Kae-Won-Seok-Kyo-Lock (개원석교록). Sok-Kae­Won-Seok-Kyo-Lock (속개원석교록). Jeong-Won-Sin-Jeong-Seok-Kyo­Lock(정원신정석교록), Sok-Jeong-Won-Seok-Kyo-Lock(속정원석교록), Dea-Jung-Sang-Bu-Beob-Bo-Lock(대중상부법보록), and Kyeong-Woo-Sin-Su-Beob-Bo-Lock(경우신수법보록), are also analysed and closely examined. The results of this study can be summarized as follows: 1. The second edition of Tripitaka Koreana(고려대장경) was carved for the purpose of defending the country from Mongolia with the power of Buddhism, after the tablets of the first edition in Buin-sa(부이사) was destroyed by fire. 2. In 1236. Dae-Jang-Do-Gam(대장도감) was established, and the preparation for the recarving of the tablets such as comparison between the content, of the first edition of Tripitalk Koreana, Gal-Bo-Chik-Pan-Dae­Jang-Kyeong and Kitan Dae- Jang-Kyeong, transcription of the original copy and the preparation of the wood, etc. was started. 3. In 1237 after the announcement of Dae-Jang-Gyeong-Gak-Pan-Gun­Sin-Gi-Go-Mun(대장경핵판군신석고문), the carving was started on a full scale. And seven years later (1243), Bun-Sa-Dae-Jang-Do-Gam(분사대장도감) was established in the area of the South to expand and hasten the work. And a large number of the tablets were carved in there. 4. It took 16 years to carve the main text and the supplements of the second edition of Tripitaka Koreana, the main text being carved from 1237 to 1248 and the supplement from 1244 to 1251. 5. It can be supposed that the tablets of the second edition of Tripitaka Koreana, stored in Seon-Won-Sa(선원사), Kang-Wha(강화), for about 140 years, was moved to Ji-Cheon-Sa(지천사), Yong-San(용산), and to Hae-In-Sa(해인사) again, through the west and the south sea and Jang-Gyeong-Po(장경포), Go-Ryeong(고령), in the autumn of the same year. 6. The second edition of Tripitaka Koreana was carved mainly based on the first edition, comparing with Gae-Bo-Chik-Pan-Dae-Jang-Kyeong(개보판대장경) and Kitan Dae-Jang-Kyeong(계단대장경). And the second edition of Dae-Jang-Mock-Lock also compiled mainly based on the first edition with the reference to Kae-Won-Seok-Kyo-Lock and Sok-Jeong-Won-Seok-Kyo-Lock. 7. Comparing with the first edition of Dae-Jang-Mock-Lock, in the second edition 7 items of 9 volumes of Kitan text such as Weol-Deung­Sam-Mae-Gyeong-Ron(월증삼매경론) are added and 3 items of 60 volumes such as Dae-Jong-Ji-Hyeon-Mun-Ron(대종지현문논) are substituted into others from Cheon chest(천함) to Kaeng chest(경함), and 92 items of 601 volumes such as Beob-Won-Ju-Rim-Jeon(법원주임전) are added after Kaeng chest. And 4 items of 50 volumes such as Yuk-Ja-Sin-Ju-Wang-Kyeong(육자신주왕경) are ommitted in the second edition. 8. Comparing with Kae-Won-Seok-Kyo-Lock, Cheon chest to Young chest (영함) of the second edition is compiled according to Ib-Jang-Lock(입장록) of Kae-Won-Seok-Kyo-Lock. But 15 items of 43 vol­umes such as Bul-Seol-Ban-Ju-Sam-Mae-Kyeong(불설반주삼매경) are ;added and 7 items of 35 volumes such as Dae-Bang-Deung-Dae-Jib-Il­Jang-Kyeong(대방등대집일장경) are ommitted. 9. Comparing with Sok-Jeong-Won-Seok-Kyo-Lock, 3 items of the 47 volumes (or 49 volumes) are ommitted and 4 items of 96 volumes are ;added in Caek chest(책함) to Mil chest(밀함) of the second edition. But the items are arranged in the same order. 10. Comparing with Dae- Jung-Sang-Bo-Beob-Bo-Lock, the arrangement of the second edition is entirely different from it. But 170 items of 329 volumes are also included in Doo chest(두함) to Kyeong chest(경함) of the second edition, and 53 items of 125 volumes in Jun chest(존함) to Jeong chest(정함). And 10 items of 108 volumes in the last part of Dae-Jung-Sang-Bo-Beob-Bo-Lock are ommitted and 3 items of 131 volumes such as Beob-Won-Ju-Rim-Jeon(법원주임전) are added in the second edition. 11. Comparing with Kyeong-Woo-Sin-Su-Beob-Bo-Lock, all of the items (21 items of 161 volumes) are included in the second edition without ;any classificatory system. And 22 items of 172 volumes in the Seong­Hyeon-Jib-Jeon(성현집전) part such as Myo-Gak-Bi-Cheon(묘각비전) are ommitted. 12. The last part of the second edition, Joo chest(주함) to Dong chest (동함), includes 14 items of 237 volumes. But these items cannot be found in any other former Buddhist catalog. So it might be supposed as the Kitan texts. 13. Besides including almost all items in Kae-Won-Seok-Kyo-Lock and all items in Sok-Jeong-Won-Seok-Kyo-Lock, Dae-Jung-Sang-Bo­Beob-Bo-Lock, and Kyeong-Woo-Sin-Su-Beob-Bo-Lock, the second edition of Dae-Jang-Mock-Lock includes more items, at least 20 items of about 300 volumes of Kitan Tripitaka and 15 items of 43 volumes of traditional Korean Tripitake that cannot be found any others. Therefore, Tripitaka Koreana can be said as a comprehensive Tripitaka covering all items of Tripitakas translated in Chinese character.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.21 no.8
• /
• pp.107-112
• /
• 2007

The flux-lock type SFCL consists of transformer with primary and secondary windings connected to a superconducting element in serial. It can be divided into the subtractive and the additive polarity windings according to the winding direction. It could change the fault current limiting characteristics according to the inductance ratio between the coil 1 and coil 2. We investigated the voltage-current characteristics of the flux-lock type SFCL according to the increment of applied voltage. When the applied voltage of the SFCL with the subtractive and the additive polarity windings was increased a initial limiting current ($I_{ini}$) and the quench time of the superconducting element were increased. The recovery time of the superconducting element was increased by increment of applied voltage. Therefore, it was confirmed that recovery characteristics in the flux-lock type SFCL were largely dependent on the consumed energy of a superconducting element because of increment of the consumption power into the superconducting element.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.7
• /
• pp.1141-1148
• /
• 2017

Generally, a thermistor made by sintering a metal oxide is widely used to measure the ambient temperature. This thermistor is widely used not only for industrial use but also for medical use because of its excellent sensitivity, durability, temperature change characteristics and low cost. In particular, the normal body temperature is 36.9 degrees relative to the armpit temperature, and it is most closely related to the circulating blood flow. Previous studies have shown that body temperature changes during biomechanical changes and body temperature changes by anomalous signs or illnesses. Therefore, in this study, we propose a Lock-In-Amp design to detect minute temperature changes of clothing and thermistor wired by a preacher as a method to regularly measure body temperature in daily life. Especially, it is designed to measure the minute resistance change of the thermistor according to body temperature change even in a low-cost microprocessor environment by using a micro-processor-based Lock-In-Amp, and a jacquard and the thermistor is arranged so as to be close to the side, so that the reference body temperature can be easily measured. The temperature was measured and stored in real time using short-range wireless communication for non - restraint temperature monitoring. A baby vest was made to verify its performance through temperature experiments for infants. The measurement of infant body temperature through the existing skin sensor or thermometer has limitations in monitoring infant body temperature for a long time without restriction. However, it can be overcome by using the embroidery fabric based micro temperature monitoring wireless monitoring device proposed in this study.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.50 no.10
• /
• pp.479-485
• /
• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.47 no.5
• /
• pp.358-363
• /
• 2019

If the EOIR equipment mounted on an unmanned aircraft transmits images and receives commands through a data link, there may be delays in data transmission depending on the transmission path of the data and the conditions of the ground equipment or wireless network. This increases the possibility of initial target LOCK-ON failure due to the difference between the time when the received image is viewed and the time when the image is taken. Therefore, this paper proposed a way to use frame indexes to synchronize with images, and to increase the success of target tracking by adding frame indexes to commands from the ground station.

• Proceedings of the KIEE Conference
• /
• 2004.11d
• /
• pp.93-96
• /
• 2004

In this paper, we analyzed the current limiting characteristics according to increase of source voltage in the flux-lock type high-Tc superconducting fault current limiter (SFCL). The flux-lock type SFCL consisted of two coils, which were wound in parallel each other through an iron core, and high-Tc superconducting (HTSC) element connected with coil 2 in series. The flux-lock type SFCL has the characteristics better in comparison with the resistive type SFCL because the fault current in the flux-lock type SFCL can be divided into two coils by the inductance ratio of coil 1 and coil 2. The fault current limiting operation of the flux-lock type SFCL can be different due to winding direction of the two coils. The winding method where the decrease of linkage flux between two coils in the accident happens is called the subtractive polarity winding and the winding method in case of the increase of linkage flux is called the additive polarity winding. The fault current limiting experiments according to the source voltage were performed for these two winding methods. Through the comparison and the analysis of the experimental data, we confirmed that the quench time was shorter, irrespective of the winding direction as the source voltage increased and that the fault current and the HTSC's resistance increased as the amplitude of the source voltage increased. The additive polarity winding made the fast quench time and the lower resistance of HTSC element in comparison with the subtractive polarity winding. The fault current of the subtractive polarity winding was larger than that of the additive polarity winding. In conclusion, we found that the additive polarity winding reduced the burden of SFCL because the quench time was shorter and the fault current was smaller than those of the subtractive polarity winding.

• Journal of KIISE:Databases
• /
• v.29 no.6
• /
• pp.464-476
• /
• 2002

Main-memory database systems which reside entire databases in main memory are suitable for high-performance real-time transaction processing. If two-phase locking(2PL) as concurrency control protocol is used for the transactions accessing main-memory databases, however, the possibility of lock conflict will be low but lock operations become relatively big overhead in total transaction processing time. In this paper, We designed a real-time static locking(RT-SL) protocol which minimizes lock operation overhead and reflects the priority of transactions and we implemented it on a main-memory real-time database system, Mr.RT. We also evaluate and compare its performance with the existing real-time locking protocols based on 2PL such as 2PL-PI and 2PL-HP. The extensive experiments reveal that our RT-SL outperforms the existing ones in most cases.

• The KIPS Transactions:PartA
• /
• v.10A no.3
• /
• pp.247-254
• /
• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• ETRI Journal
• /
• v.29 no.6
• /
• pp.716-724
• /
• 2007

As ultra-wideband impulse radio (UWB-IR) uses short-duration impulse signals of nanoseconds, even a small number of timing errors can cause a detrimental effect on system performance. A delay-locked loop (DLL) is proposed to synchronize and reduce timing errors. The design of the DLL is vital for UWB systems. In this paper, an improved DLL is introduced to a UWB-IR time-hopping spread-spectrum system. Instead of using only two central correlator branches as in a conventional DLL, the proposed system uses two additional correlator branches with different delay parameters and different weight parameters. The performance of the proposed schemes with the optimal parameters is compared with that of traditional schemes through simulation: the proposed four-branch DLLs achieves less tracking jitter or a longer mean time to lose lock (MTLL) than the conventional two-branch DLLs if proper parameters are chosen.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.691-693
• /
• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.