• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This paper presents a fast full search algorithm for motion estimation applicable to multiple reference images. The proposed method is an extended version of the rate constrained successive elimination algorithm (RSEA) for multiple reference frame applications. We will show that motion estimation for the reference images temporally preceding the first reference image can be less intensive in computation compared with that for the first reference image. for computational reduction, we will drive a new condition to lead the smaller number of candidate blocks for the best matched block. Simulation results explain that our method reduces computation complexity although it has the same quality as RSEA.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of the Korean Society of Costume
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• v.50 no.4
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• pp.5-20
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• 2000

Through his geometric design, the Cyprus born fashion designer Hussein Chalayan raises intriguing questions about the very fact of wearing clothes. By purposefully displacing the function of each part of the clothing, such as neck line, hem line, seam, sleeve, etc., Chalayan transforms the meaning of the body that wears clothes. of the human subject as a sovereign possessor of the clothing and the visibility related to fashion. This transformation is achieved by distorting the spaces of his clothing in an unorthodox way. This thesis argues that the significance of such a practice can not be properly understood without relation to the current debate on deconstructionism under way in humanities. Instead of immediately negating the modern frame of Ideas and practices, deconstructionism asks what the assumptions for the modern regime of truth is. In this process, things that lead human beings to sovereign master of knowledge and truth such as reason, subject, body and vision are questioned. In the same context, Chalayan's design not only forces us to rethink the very function of dividing inside and outside by the clothing but also the meaning of boundary operating in numerous sites of modern life. As the human subject is not something pre-given but constructed according to the cultural representation, to which the clothing belongs, fashion can be evaluated to be an active ingredient of constructing the subject. Therefore, Hussein Chalayan's design is at the cross road between the modern and the postmodern regime of fashion.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Structural Engineering and Mechanics
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• v.30 no.2
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• pp.191-209
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• 2008

A structural monitoring system based on cheap and wireless monitoring system is investigated in this paper. Due to low-cost and low power consumption, micro-electro-mechanical system (MEMS) is suitable for wireless monitoring and the use of MEMS and wireless communication can reduce system cost and simplify the installation for structural health monitoring. For system identification using wireless MEMS, a finite element (FE) model updating method through correlation with the initial analytical model of the structure to the measured one is used. The system identification using wireless MEMS is evaluated experimentally using a three storey frame model. Identification results are compared to ones using data measured from traditional accelerometers and results indicate that the system identification using wireless MEMS estimates system parameters with reasonable accuracy. Another smart sensor considered in this paper for structural health monitoring is Lead Zirconate Titanate (PZT) which is a type of piezoelectric material. PZT patches have been applied for the health monitoring of structures owing to their simultaneous sensing/actuating capability. In this paper, the system identification for building structures by using PZT patches functioning as sensor only is presented. The FE model updating method is applied with the experimental data obtained using PZT patches, and the results are compared to ones obtained using wireless MEMS system. Results indicate that sensing by PZT patches yields reliable system identification results even though limited information is available.

• Journal of the korean society of oceanography
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• v.38 no.4
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• pp.166-172
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• 2003

Multi­Sensor Core Logger (MSCL) is a useful system for logging the physical properties (compressional wave velocity, wet bulk density, fractional porosity, magnetic susceptibility and/or natural gamma radiation) of marine sediments through scanning of whole cores in a nondestructive fashion. But MSCL has a number of problems that can lead to spurious results depending on the various factors such as core slumping, gas expansion, mechanical stretching, and the thickness variation of core liner and sediment. For the verification of MSCL data, compressional wave velocity, wet bulk density, and porosity were measured on discrete samples by Hamilton Frame and Gravimetric method, respectively. Acoustic impedance was also calculated. Physical property data (velocity, wet bulk density, and impedance) logged by MSCL were slightly larger than those of discrete sample, and porosity is reverse. Average difference between MSCL and discrete sample at both sites is relatively small such as 22­24 m/s in velocity, $0.02­-0.08\;g/\textrm{cm}^3$ in wet bulk density, and 2.5­2.7% in porosity. The values also show systematic variation with sediment depth. A variety of factors are probably responsible for the differences including instrument error, various measurement method, sediment disturbance, and accuracy of calibration. Therefore, MSCL can be effectively used to collect physical property data with high resolution and quality, if the calibration is accurately completed.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.126-132
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• 2005

In this paper, an auto-design system is introduced for a stamping tool based on commercial computer aided design system with its drafting language. The auto-design system consists of tool oriented product design subsystem which modifies and configures the product drawing, tool concept design subsystem which make a design of the punches and their punching progression and parts design subsystem that makes automatic dimension. The system is applied to the mechanical design of the stamping tool. The main logic of the system is based on half-edge theory, a kernel for the 3 dimensional CAD system, which is applied to 2 dimensional drafting auto-design system. The auto-design system enables to conspicuously reducing the designing time of the tool. In addition, there is little drafting error that had been about 3% without auto design program. It is effective to reduce the development time for new products because of rapid designing time of the tools, standardization of the stamping tool and the drafting rule for the auto-design system. The auto-design system yields high efficiency of the tool manufacturing system.

• Korean Journal of Materials Research
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• v.13 no.2
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• pp.133-136
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• 2003

Sn-2.5Cu alloy layers were deposited on the Alloy 42 lead-frame substrates by the electroplating method, and their microstructures, adhesion strength, and electrical resistivity were measured to evaluate the applicability of Sn-Cu alloy as a surface finishing material of electronic parts. The Sn-2.5Cu layers were electroplated in the granular form, and composed of pure Sn and Cu$_{6}$Sn$_{5}$ intermetallic compound. Surfaces of the electroplated Sn-2.5Cu layers were rather rough and also the thickness variance was large. The adhesion strength of the Sn-2.5Cu electroplated layers was highly comparable to that of the electroplated Cu alloy layer and the electrical conductivity was about 10 times higher than the pure Sn. After the 20$0^{\circ}C$ 30 min. annealing of the electroplated Sn-2.5Cu layers, the surface roughness was reduced, and adhesion strength and conductivity were improved. These results showed the Sn-Cu alloys can be used as an excellent surface finishing material.ial.

• Earthquakes and Structures
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• v.9 no.6
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• pp.1337-1353
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• 2015

Seismic upgrading of existing structures is a technical and social issue aimed at risk reduction. Sustainable design is one of the most important challenges in any structural project. Nowadays, many retrofit strategies are feasible and several traditional and innovative options are available to engineers. Basically, the design strategy can lead to increase structural ductility, strength, or both of them, but also stiffness regulation and supplemental damping are possible strategies to reduce seismic vulnerability. Each design solution has different technical and economical performances. In this paper, four different design solutions are presented for the retrofit of an existing RC frame with poor concrete quality and inadequate reinforcement detailing. The considered solutions are based on FRP wrapping of the existing structural elements or alternatively on new RC shear walls introduction. This paper shows the comparison among the considered design strategies in order to select the suitable solution, which reaches the compromise between the obtained safety level and costs during the life-cycle of the building. Each solution is worked out by considering three different levels of seismic demand. The structural capacity of the considered retrofit solutions is assessed with nonlinear static analysis and the seismic performance is evaluated with the capacity spectrum method.