• Journal of Broadcast Engineering
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• v.27 no.1
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• pp.146-149
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• 2022

In this letter, we propose low-complexity Hybrid-Partial-Gaussian-Approximation (HPGA) decoding methods for core-layer signal of Layered-Division-Multiplexing Multiple-Inputs-Multiple- Outputs ATSC 3.0 broadcasting systems. The proposed HPGA decoding methods have an advantage of being able to greatly reduce decoding complexity without significant performance degradation compared to a conventional PGA method, by selectively using existing GA and PGA methods according to a received injection-level at an each receive antenna.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.1-5
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• 2008

In this paper, we propose and analyze the AMC (Adaptive Modulation and Coding) system with efficient turbo coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique. The proposed algorithm adopts extrinsic information from a MAP (Maximum A Posteriori) decoder with iterative decoding as a priori probability in two decoding procedures of V-BLAST scheme; the ordering and the slicing. Also, we consider the AMC system using the conventional turbo coded V-BLAST technique that simply combines the V-BLAST scheme with the turbo coding scheme. And we compare the proposed decoding algorithm to a conventional V-BLAST decoding algorithm and a ML (Maximum Likelihood) decoding algorithm. In addition, we apply a STD (Selection Transmit Diversity) scheme to the systems for better performance improvement. Results indicate that the proposed systems achieve better throughput performance than the conventional systems over the entire SNR range. In terms of transmission rate performance, the suggested system is close in proximity to the conventional system using the ML decoding algorithm.

• Journal of Broadcast Engineering
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• v.24 no.6
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• pp.1072-1075
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• 2019

In this letter, we propose a new soft decoding method for a Core-Layer(CL) signal in ATSC3.0 Layered-Division-Multiplexing Multiple-Inputs-Multiple-Outputs broadcasting systems. Unlike a conventional Gaussian-Approximation(GA) method, the proposed method decodes the CL signal by reducing a Enhanced-Layer signal simply to a QPSK signal, and thus exhibits greatly improved performance compared to the GA method especially for a lower CL injection-level.

• Journal of Communications and Networks
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• v.8 no.3
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• pp.275-285
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• 2006

Suitable for multi-input multi-output (MIMO) communications, the joint beamforming space-time block coding (JBSTBC) scheme is proposed for high-speed downlink transmission. The major functionality of the scheme entails space-time block encoder and joint transmit and receive eigen-beamformer (EBF) incorporating with block-ordered layered decoder (BOLD), and its operating principle is described in this paper. Within these functionalities, the joint EBFs will be utilized for decorrelating fading channels to cause an enhancement in the spatial diversity gain. Furthermore, to fortify the capability of layered successive interference cancellation (LSIC) in block-ordered layered decoding process, this paper will develop a simple ad-hoc transmit power discrimination scheme (TPDS) based on a particular power discrimination function (PDF). To confirm the superior behavior of the proposed JBSTBC scheme employing ad-hoc TPDS, computer simulations will be conducted under various channel conditions with the provision of detailed mathematical derivations for clarifying its functionality.

• ETRI Journal
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• v.26 no.5
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• pp.384-390
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• 2004

We propose a new bandwidth-efficient technique that achieves high data rates over a wideband wireless channel. This new scheme is targeted for a multiple-input multiple- output orthogonal frequency-division multiplexing (MIMO-OFDM) system that achieves transmit diversity through a space frequency block code and capacity enhancement through the iterative joint processing of zero-forcing detection and maximum a posteriori (MAP) decoding. Furthermore, the proposed scheme is compared to the coded Bell Labs Layered Space-Time OFDM (BLAST-OFDM) scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.229-232
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• 2012

This paper describes performance evaluation using fixed-point Matlab modeling and simulation, and hardware design of LDPC decoder which is based on Improved Normalized Min-Sum(INMS) decoding algorithm. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard. Considering hardware complexity, it is designed using a block-serial(partially parallel) architecture which is based on layered decoding scheme. A DFU based on sign-magnitude arithmetic is adopted to minimize hardware area. Hardware design is optimized by using INMS decoding algorithm whose performance is better than min-sum algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.385-391
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• 2007

In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP (Maximum A Posteriori) Decoder with Iterative Decoding to use as a priori probability in two decoding procedures of V-BLAST: ordering and slicing. Also, comparing with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance has been improved. As a result of simulation, in the Adaptive Modulation systems with several Turbo Coded V-BLAST techniques, the optimal Turbo Coded V-BLAST technique has higher throughput gain than the conventional Turbo Coded V-BLAST technique. Especially, the results show that the proposed scheme achieves the gain of 1.5 dB SNR compared to the conventional system at 2.5 Mbps throughput.