• Title/Summary/Keyword: lateral asymmetric channel doping

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Device Optimization of N-Channel MOSFETs with Lateral Asymmetric Channel Doping Profiles

  • Baek, Ki-Ju;Kim, Jun-Kyu;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.15-19
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    • 2010
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

Preparation of Epoxy/Organoclay Nanocomposites for Electrical Insulating Material Using an Ultrasonicator

  • Park, Jae-Jun;Park, Young-Bum;Lee, Jae-Young
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.3
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    • pp.93-97
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    • 2011
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

Sensing Properties of Ga-doped ZnO Nanowire Gas Sensor

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.2
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    • pp.78-81
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    • 2015
  • Pure ZnO and ZnO nanowires doped with 3 wt.% Ga (‘3GZO’) were grown by pulsed laser deposition in a furnace system. The doping of Ga in ZnO nanowires was analyzed by observing the optical and chemical properties of the doped nanowires. The diameter and length of nanowires were under 200 nm and several ${\mu}m$, respectively. Changes of significant resistance were observed and the sensitivities of ZnO and 3GZO nanowires were compared. The sensitivities of ZnO and 3GZO nanowire sensors measured at 300℃ for 1 ppm of ethanol gas were 97% and 48%, respectively.

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

  • Sahu, P.K.;Mohapatra, S.K.;Pradhan, K.P.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.6
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    • pp.647-654
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    • 2013
  • The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

Comparison of Drain-Induced-Barrier-Lowering (DIBL) Effect by Different Drain Engineering

  • Choi, Byoung-Seon;Choi, Pyung-Ho;Choi, Byoung-Deog
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.342-343
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    • 2012
  • We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

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Characterization of Ultra Low-k SiOC(H) Film Deposited by Plasma-Enhanced Chemical Vapor Deposition (PECVD)

  • Kim, Sang-Yong
    • Transactions on Electrical and Electronic Materials
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    • v.13 no.2
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    • pp.69-72
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    • 2012
  • In this study, deposition of low-dielectric constant SiOC(H) films by conventional plasma-enhanced chemical vapor deposition (PECVD) were investigated through various characterization techniques. The results show that, with an increase in the plasma power density, the relative dielectric constant (k) of the deposited films decreases whereas the refractive index increases. This is mainly due to the incorporation of organic molecules with $CH_3$ group into the Si-O-Si cage structure. It is as confirmed by FT-IR measurements in which the absorption peak at 1,129 $cm^{-1}$ corresponding to Si-O-Si cage structure increases with power plasma density. Electrical characterization reveals that even after fast thermal annealing process, the leakage current density of the deposited films is in the order of $10^{-11}$ A/cm at 1.5 MV/cm. The reliability of the SiOC(H) film is also further characterized by using BTS test.

Effect of Electric Field Frequency on the AC Electrical Treeing Phenomena in an Epoxy/Reactive Diluent/Layered Silicate Nanocomposite

  • Park, Jae-Jun
    • Transactions on Electrical and Electronic Materials
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    • v.15 no.2
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    • pp.87-90
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    • 2014
  • The effects of electric field frequency on the ac electrical treeing phenomena in an epoxy/reactive diluent/layered silicate (1.5 wt%) were carried out, in needle-plate electrode arrangement. A layered silicate was exfoliated in an epoxy base resin, by using our ac electric field apparatus. To measure the treeing propagation rate, constant alternating current (AC) of 10 kV with three different electric field frequencies (60, 500 and 1,000 Hz) was applied to the specimen, in needle-plate electrode arrangement, at $30^{\circ}C$ of insulating oil bath. As the electric field frequency increased, the treeing propagation rate increased. At 500 Hz, the treeing propagation rate of the epoxy/PG/nanosilicate system was $0.41{\times}10^{-3}$ mm/min, which was 3.4 times slower than that of the epoxy/PG system. The electrical treeing morphology was dense bush type at 60 Hz; however, as the frequency increased, the bush type was changed to branch type, having few branches, with very slow propagation rate.