• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.460-462
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• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• 대한전자공학회논문지SD
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• 제39권10호
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• pp.25-34
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• 2002

본 논문에서는 코발트 실리사이드가 형성된 얕은 p+-n과 n+-p 접합의 전류-전압 특성을 분석하여 silicidation에 의해 형성된 Schottky contact 면적을 구하였다. 역방향 바이어스 영역에서는 Poole-Frenkel barrier lowering 효과가 지배적으로 나타나서 Schottky contact 효과를 파악하기가 어려웠다. 그러나 Schottky contact의 형성은 순방향 바이어스 영역에서 n+-p 접합의 전류-전압 (I-V) 동작에 영향을 미치는 것으로 확인되었다. 실리사이드가 형성된 n+-p 다이오드의 누설전류 증가는 실리사이드가 형성될 때 p-substrate또는 depletion area로 코발트가 침투퇴어 Schottky contact을 형성하거나 trap들을 발생시켰기 때문이다. 분석결과 perimeter intensive diode인 경우에는 silicide가 junction area까지 침투하였으며, area intensive junction인 경우에는 silicide가 비록 공핍층이나 p-substrate까지 침투하지는 않았더라도 공핍층 근처까지 침투하여 trap들을 발생시켜 누설전류를 증가시킴을 확인하였다. 반면 p+-n 다이오드의 경우 Schottky contact이발생하지 않았고 따라서 누설전류도 증가하지 않았다. n+-p 다이오드에서 실리사이드에 의해 형성된 Schottky contact 면적은 순방향 바이어스와 역방향 바이어스의 전류 전압특성을 동시에 제시하여 유도할 수 있었고 전체 접합면적의 0.01%보다 작게 분석되었다.

• 한국전기전자재료학회논문지
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• 제13권1호
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• pp.13-20
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• 2000

In this paper, we demonstrated an analytical description method of forward votage drop and reverse leakage current of the junction barrier controlled schottky rectifier with linearly graded junction and abrupt junction models. In this case, the vertical depths of device are 1[${\mu}{\textrm}{m}$] and 2[${\mu}{\textrm}{m}$], respectively. Through ion implantation and annealing process, we obtain the data of lateral and depth from implanted 2-dimensional profiles. Also we applied these data to models that indicate the change of depletion each on linearly-graded and abrupt juction as the forward and revers bias. After applied depletion changes to electric characteristics of JBS rectifiers, we calculated the forward I-V, the reverse leakage current and temperatures vs. power dissipations according to each junction. When we compared the rectifier with calculated and measured data, from the calculated results, forward votage drop with linearly graded junction is lower than that of abrupt junction and reverse leakage current with linearly graded junction is lower(≒1$\times$10\ulcorner times) than that of abrupt junction. Also, the power dissipations according to different juction depth(1[${\mu}{\textrm}{m}$], 2[${\mu}{\textrm}{m}$]) of device are calculated. Seeing the calculated results, we confirmed it from analytic model that the rectifier with linearly graded junction retained a low power dissipation up to 600[$^{\circ}C$] in comparison with the rectifier with abrupt junction.

• 한국전기전자재료학회논문지
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• 제13권11호
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• pp.908-913
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• 2000

CoSi$_2$/p+/n diodes(bilayer diodes) were fabricated by using epitaxial CoSi$_2$grown from Co/Ti bilayer as a diffusion source. The I-V characteristics of p+/n diodes were measured and compared with those of diode made from Co monolayer (monolayer diode). Monolayer diodes showed typical p+n junction characteristics with the leakage current of as low as 10$^{-12}$ A and forward current 6-orders higher than the leakage current, when drive-in annealed at 90$0^{\circ}C$ for 20 sec.. On the other hand, bilayer diodes showed the Schottky-like behaviors with forward currents rather higher than those of monolyer diodes, but with too high leakage currents, when drive-in annealed at $700^{\circ}C$ or higher. However, when the annealing temperature was lowered to $700^{\circ}C$ and annealing time was increased to 60 sec., the leakage current was reduced to 10$^{-11}$ A and thus sho3wed typical diode characteristics. The high leakage currents for diodes annealed at $700^{\circ}C$ or higher was attributed to Shannon contacts formed due to unremoved Co-Ti-Si precipitates. But when annealed at 50$0^{\circ}C$, B ions diffused in the direction of the surface layer, and thus the leakage currents were reduced by removing Shannon contacts.

• 전자공학회논문지A
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• 제31A권5호
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• pp.94-100
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• 1994

The junction failure mechanism of W plugs has not been fully understood while the selective W deposition has been widely used for plugging interconnection lines. In this paper, the thermal stability and junction failure mechanism of sub-micron contacts using selective CVD-W plugs were intensively studied with the metal lines of AISiCu, Ti/AISiCu and TiN/AISiCu. The experimental results showed that the contact chain resistance and leakage current in the AISiCu and Ti/AISiCu metallizations were significantly degraded after annealing. From the SEM analysis, it was found that the junction spiking, due to the Al atoms diffusion along the porous interface between selective CVD-W and contactside wall, caused the junction failure. In constast, there was no degradation of the contact resistance and junction leakage current in TiN/AISiCu metal structu-re. It is believed that the TiN barrier layer could prevent AI(Ti) atoms Fromdiffusing. Therefore, TiN barrier between W plug and Al should be used to impro-ve the thermal stability of sub-micron contacts using the selective CVD-W plugs.

• 한국재료학회지
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• 제24권9호
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• pp.502-507
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• 2014

Recently, improvement in the conversion efficiency of silicon-based solar cells has been achieved by decreasing emitter doping concentration, because the lightly doped emitter can effectively prevent the recombination of electrons and holes generated by solar light irradiation. This type of emitter is very thin due to the low doping concentration, thus conductive materials (i.e., silver) used for front electrodes can easily penetrate the emitter during a firing process because of their large diffusivity in silicon. This results in junction leakage currents which might reduce cell efficiencies. In this study, $Al_2O_3$-coated Ag powders were synthesized by an ultrasonic spray pyrolysis method and applied to the conductive materials of the front electrode to control the junction leakage current. The $Al_2O_3$ shell obstructs the Ag diffusion into the emitter during the firing process. The powder is spherical with a core-shell structure and the thickness of the $Al_2O_3$ shell is tens of nanometers. Solar cells were fabricated using pure Ag powders or the $Al_2O_3$-coated Ag powder as front electrode materials, and the conversion efficiency and junction leakage current were compared to investigate the role of the $Al_2O_3$ shell during the firing processes.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.237-240
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• 2002

In this W, a NiSi technology suitable for sub-100nm CMOS sevice is proposed. It seems that capping layer has little effect on the sheet resistance and junction leakage current when there is no thermal treatment. However, there happened agglomeration and drastic increase of Junction leakage current without capping layer. In other word, capping layer especially TiN capping layer is highly effective in suppressing thermal effect. It is shown that the sheet resistance of 0.12${\mu}{\textrm}{m}$ linewidth and shallow p+/n junction with NiSi were stable up to 700 t /30 minute thermal treatment.

• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.111-116
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• 2001

Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

• 전자공학회논문지A
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• 제33A권7호
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.

• ETRI Journal
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• 제38권2호
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• pp.244-251
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• 2016

In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs' electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ($V_F$) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode.like properties, such as a high $V_F$, low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time.