• Clean Technology
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• v.28 no.3
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• pp.227-231
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• 2022

The demand for high-voltage power devices is rising in various industries, but especially in the transportation industry due to autonomous driving and electric vehicles. IGBT module parts of 3.3 kV or more are used in the power propulsion control device of electric vehicles, and the procurement of these parts for new construction and maintenance is increasing every year. In addition, research to optimize high-voltage IGBT parts is urgently required to overcome their very high technology entry barrier. For the development of high-voltage IGBT devices over 3.3 kV, the resistivity range setting of the wafer and the optimal conditions for major unit processes are important variables. Among the manufacturing processes to secure the optimal junction depth, the optimization of the diffusion process, which is one step of the unit process, was examined. In the diffusion process, the type of gas injected, the injection time, and the injection temperature are the main variables. In this study, the range of wafer resistance (Ω cm) was set for the development of high voltage IGBT devices through unit process simulation. Additionally, the well drive in (WDR) condition optimization of the diffusion process according to temperature was studied. The junction depth was 7.4 to7.5 ㎛ for a ring pattern width of 23.5 to25.87 ㎛, which can be optimized for supporting 3.3 kV high voltage power devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.4
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• pp.210-213
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• 2017

In this paper, we analyzed the structural design and electrical characteristics of a 3.3 kV super junction FS IGBT as a next generation power device. The device parameters were extracted by design and process simulation. To obtain optimal breakdown voltage, we researched the breakdown characteristics. Initially, we confirmed that the breakdown voltage decreased as trench depth increased. We analyzed the breakdown voltage according to p pillar dose. As a result of the experiment, we confirmed that the breakdown voltage increased as p pillar dose increased. To obtain more than 3.3 kV, the p pillar dose was $5{\times}10^{13}cm^{-2}$, and the epi layer resistance was $140{\Omega}$. We extracted design and process parameters considering the on state voltage drop.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.187-191
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• 2004

In this work, we used the PCID simulator for simulation of solar cell and examined the effect of front-back surface recombination velocity, minority carrier diffusion length, junction depth and emitter sheet-resistance. As the effect of base thickness, the efficiency decreased by the increase in series resistance with the increase of the thickness and found decrease in efficiency by decrease of the current as the effect of the recombination. Also, as the effect of base resistivity, the efficiency increased somewhat with the decrease in resistivity, but when the resistivity exceeded certain value, the efficiency decreased as a increase in the recombination ratio. The optimum efficiency was obtained at the resistivity 0.5 $\Omega$-cm, and thickness $100\mu\textrm{m}$. We have successfully achieved 10.8% and 13.7% efficiency large area($103mm{\times}103mm$) mono-crystalline silicon solar cells without and with PECVD silicon nitride antireflection coating.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.53.1-53.1
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• 2010

결정질 실리콘 태양전지의 효율을 향상시키기 위하여 수광면에 서로 다른 도핑농도를 가지는 고농도 도핑영역과 저농도 도핑영역으로 이루어진 emitter를 형성하는 것이 요구되며 이를 selective emitter라 칭한다. Selective emitter를 형성하면 고농도 도핑영역에서 금속전극과 저항 접촉이 잘 형성되기 때문에 직렬 저항이 최소화되고 저농도 도핑영역에서는 전하 재결합의 감소로 인하여 태양전지의 변환효율이 상승하는 이점이 있다. Selective emitter의 형성방법은 이미 다양한 방법이 제안되고 있으나, 본 연구에서는 기존에 제시된 방법과는 다르게 열산화 시 dopant redistribution에 의한 Boron depletion 현상을 이용하여 selective emitter를 형성하는 방법을 제안하였고, 이를 Simulation을 통하여 검증하였다. 초기 emitter 확산 후 junction depth는 0.478um, 면저항은 $104.2{\Omega}/sq.$ 이었으며, nitride masking layer 두께는 0.3um로 설정하였다. $1100^{\circ}C$에서 30분간 습식산화 공정을 거친 후 nitride mask가 있는 부분의 junction depth는 1.48um, 면저항은 $89.1{\Omega}/sq$의 값을 보였고, 산화막이 형성된 부분의 junction depth는 1.16um, 면저항은 $261.8{\Omega}/sq$의 값을 보였다. 위 조건의 구조를 가진 태양전지의 변환 효율은 19.28%의 값을 나타내었고 Voc, Jsc 및 fill factor는 각각 645.08mV, $36.26mA/cm^2$, 82.42%의 값을 보였다. 한편 일반적인 구조로 설정한 태양전지의 변환 효율, Voc, Isc 및 fill factor는 각각 18.73%, 644.86mV, $36.26mA/cm^2$, 80.09%의 값을 보였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.80-90
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• 1994

The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).