• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.1-10
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• 1999

A low power concumption 2.4 GHz one-chip transceiver MMIC was designed and fabricated using $1.0\mu\textrm{m}$ ion-implantation MESFET process and packaged on a 24 lead SSOP. In the transmitter mode, it revealed conversion gain of 7.5 dB, output IP3 of -3.5 dBm, and noise figure of 3.9 dB at 2.44 GHz with 3.9 mA current consumption. In the receiver mode, it revealed voltage sensitivity of 6.5 mV/$\mu\$W with 2 .0 mA current consumption. Comparing the fabricated MMIC with the results of MMICs reported elsewhere, it was shown that the fabricated MMIC had good performance. The low power consumption 2.4 GHz transceiver MMIC is expected to be used for various applications such as wireless local area networks, wireless local loops and RFID tags in ISM-band.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.6-14
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• 2012

For integrated complementary metal oxide semiconductor (CMOS) circuits, the lateral spread for two-dimensional (2-D) impurity distributions are very important for the analyzing the devices. The measured two-dimensional SEM data obtained using the chemical etching-method matched very well with the results of the Gauss model for boron implanted samples. But the profiles in boron implanted silicon were deviated from the Gauss model. The profiles in boron implanted silicon were shown a little bit steep profile in the deep region due to backscattering effect on the near surface from the bombardments of light boron ions. From the simulated 3-D data obtained using an analytical model, the 1-D and 2-D data were compared with the experimental data and could be verified the justification from the experimental data. The data of 3-D model were also shown good agreements with the experimental and the simulated data. It can be used in the 3-D chip design and the analysis of microelectro-mecanical system (MEMS) and special devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.3
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• pp.248-251
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• 2009

We have investigated the effect of the quality of 1.3 um distributed feed back laser diode (DFB-LD) on the design of anti-reflection (AR) coatings. Optimal condition of AR coating to prevent internal feedback from both facets and reduce the reflection-induced intensity noise of laser diode was simulated with Macleod Simulator. Coating materials used in this work were ${Ti_3}{O_5}$ and $SiO_2$, of which design thickness were 105 nm and 165 nm, respectively. AR coating films were deposited by Ion-Assisted Deposition system. The electrical and optical properties of 1.3 um laser diode were characterized by Bar tester and Chip tester. Threshold current and slop-efficiency of DFB-LD were 27.56 mA 0.302 W/A. Far field pattern and wavelength of DFB-LD were $22.3^{\circ}(Horizontal){\times}24.4^{\circ}$ (Vertical), 1313.8 nm, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.911-915
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• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.22-25
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• 2020

Deep red EuSi₂O₂N₂ phosphors were synthesized under various sintering gas pressures (1 atm, 2 atm, and 3 atm). They were in good agreement with the standard EuSi₂O₂N₂ ICSD card # 41-6046 (a monoclinic crystal system with space group of P2₁/a). Their photoluminescence intensities were significantly increased with increasing the gas pressures. They showed a broad band emission peaking at 680 nm due to 4f⁶5d¹ - 4f⁷ of Eu²⁺ ion, which can be efficiently excited in the visible range up to 550 nm. The best one at 3 atm was applied for red LED based on blue chip, which showed the strong deep red emission.

• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.36-43
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• 2013

In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.571-572
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• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.22 no.1
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• pp.52-59
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• 2012

Objectives: The purpose of this study was to evaluate the exposure possibility of by-products during the semiconductor manufacturing processes. Methods: The authors investigated types of chemicals generated during semiconductor manufacturing processes by the qualitative experiment on generation of by-products at the laboratory and a literature survey. Results: By-products due to decomposition of photoresist by UV-light during the photo-lithography process, ionization of arsine during the ion implant process, and inter-reactions of chemicals used at diffusion and deposition processes can be generated in wafer fabrication line. Volatile organic compounds (VOCs) such as benzene and formaldehyde can be generated during the mold process due to decomposition of epoxy molding compound and mold cleaner in semiconductor chip assembly line. Conclusions: Various types of by-products can be generated during the semiconductor manufacturing processes. Therefore, by-products carcinogen such as benzene, formaldehyde, and arsenic as well as chemical substances used during the semiconductor manufacturing processes should be controlled carefully.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• Clean Technology
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• v.29 no.4
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• pp.255-261
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• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.