• Title/Summary/Keyword: internal memory

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Analysis of 3-D non-linear truss smart actuator using SMA (형상기억합금을 이용한 3 차원 비선형 트러스 지능작동기 해석)

  • Yang, Seong-Pil;Kim, Sang-Haun;Li, Ningxue;Ryu, Jung-Hyun;Cho, Maeng-Hyo
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2008.04a
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    • pp.557-561
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    • 2008
  • Shape memory alloys (SMA) have interesting features which are the superelastic effect (SE), shape memory effect (SME), two-way SME (TWSME), and so on. These are utilized in actuation factor. The thermo-mechanical constitutive equations of SMA proposed by Lagoudas et al. were employed in the present study for simulating SMA truss structures. The constitutive equation includes the necessary internal variables to account for the material transformations and is utilized in the non-linear finite element procedure of three dimensional truss structures that composed SMA bar (wholly or partially). In this study, we observed which element should be actuated to get a desired shape (actuation shape) from computational analysis. To reach this goal, we apply SMA constitutive equation to non-linear finite element formulation. And then, we simulate two-way shape memory effect as well as superelastic effect of various three dimensional truss using SMA.

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An Improved Constitutive Model of Shape Memory Alloy (형상기억합금의 개선된 구성적 모델)

  • Ho, Kwang-Soo
    • Transactions of Materials Processing
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    • v.20 no.5
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    • pp.350-356
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    • 2011
  • Shape memory alloys(SMAs) exhibit pseudoelastic behavior, characterized by the recovery of an original shape even after severe deformation, during loading and unloading within appropriate temperature regimes. The distinctive mechanical behavior is associated with stress-induced transformation of austenite to martensite during loading and reverse transformation to austenite upon unloading. To develop a material model for SMAs, it is imperative to consider the difference in moduli of active phases. For example, the Young’s modulus of the martensite is one-third to one half of that of the austenite. The model proposed herein is a modification of the one proposed recently by Ho[17]. The prediction of the behavior of SMAs during unloading before the onset of reverse transformation was improved by introducing a new internal state variable incorporating the variation of the elastic modulus.

A Multicast ATM Switch Architecture using Shared Bus and Shared Memory Switch (공유 버스와 공유 메모리 스위치를 이용한 멀티캐스트 ATM 스위치 구조)

  • 강행익;박영근
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.8B
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    • pp.1401-1411
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    • 1999
  • Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

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Multi-layered attentional peephole convolutional LSTM for abstractive text summarization

  • Rahman, Md. Motiur;Siddiqui, Fazlul Hasan
    • ETRI Journal
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    • v.43 no.2
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    • pp.288-298
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    • 2021
  • Abstractive text summarization is a process of making a summary of a given text by paraphrasing the facts of the text while keeping the meaning intact. The manmade summary generation process is laborious and time-consuming. We present here a summary generation model that is based on multilayered attentional peephole convolutional long short-term memory (MAPCoL; LSTM) in order to extract abstractive summaries of large text in an automated manner. We added the concept of attention in a peephole convolutional LSTM to improve the overall quality of a summary by giving weights to important parts of the source text during training. We evaluated the performance with regard to semantic coherence of our MAPCoL model over a popular dataset named CNN/Daily Mail, and found that MAPCoL outperformed other traditional LSTM-based models. We found improvements in the performance of MAPCoL in different internal settings when compared to state-of-the-art models of abstractive text summarization.

An Analysis of Memory Access Complexity for HEVC Decoder (HEVC 복호화기의 메모리 접근 복잡도 분석)

  • Jo, Song Hyun;Kim, Youngnam;Song, Yong Ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.5
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    • pp.114-124
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    • 2014
  • HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

The Efficacy of Oriental Medicine on Memory in Menopause: A Systemic Review (폐경기 기억력에 대한 한약의 효과 : 체계적 문헌고찰)

  • Soo-Hyung Lee;Ha-Rin Kwon;In-Jeong Jo;Se-Eun Chun;Song-Baek Kim
    • The Journal of Korean Obstetrics and Gynecology
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    • v.36 no.2
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    • pp.20-35
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    • 2023
  • Objectives: The purpose of this study is to review clinical studies and investigate the efficacy and safety of oriental medicine on memory in menopausal women. Methods: 'menopause', 'memory', 'oriental medicine' were searched on 4 online databases (Cochrane Library, Pubmed, CNKI, OASIS). Randomized controlled trials (RCTs) that evaluated menopausal memory with oriental medicine treatment were included. The methodological quality of each RCT was assessed by using Cochrane risk of bias tool. Results: 8 RCTs were selected among 1067 articles. The overall risk of bias was evaluated as uncertain. 5 studies showed that oriental medicine alone was significant effective, but 1 long-term study with the same oriental medicine did not sustain the effect, and 2 studied were not statistically significant. Conclusions: Oriental medicine can be an effective option for improving memory in menopausal women. but considering the small number and quality of studies, inconsistent and insufficient evidence, further well-designed studies are needed to confirm the efficacy and safety of this treatment.

A Fast Processor Architecture and 2-D Data Scheduling Method to Implement the Lifting Scheme 2-D Discrete Wavelet Transform (리프팅 스킴의 2차원 이산 웨이브릿 변환 하드웨어 구현을 위한 고속 프로세서 구조 및 2차원 데이터 스케줄링 방법)

  • Kim Jong Woog;Chong Jong Wha
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.19-28
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    • 2005
  • In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

A clinical study on the prodromal syndrome of cerebral infarction (뇌경색환자(腦梗塞患者)의 중풍전조증(中風前兆症)에 대한 임상적(臨床的) 고찰(考察))

  • Seo, Chang-Hoon;Kwon, Jung-Nam
    • The Journal of Internal Korean Medicine
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    • v.19 no.1
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    • pp.134-143
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    • 1998
  • Background : The purpose of this study was to investigate the prodromal of cerebral infarction in attacked patients and to prove the traditional hypothesis that some symptoms were to be prodromes of cerebral infarction in the oriental medicine. Methods : The questionnaire which was based on symptoms of traditional hypothesis was distributed cerebral infarction patients who were confirmed by Brain CT or MRI.. Results : Fifty-six patients(93.3%) felt some symptoms within three years before onset. Most common prodromal symptoms was dizziness(50%), failure of memory(45%), numbness of arm(45%). Conclusion : This results suggest that the prodromal symptoms before cerebral infarction can be regarded as predicting sign. and we think that these research may contributed to preventing stroke and relapse.

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Design of a Sense Amplifier Minimizing bit Line Disturbance for a Flash Memory (비트라인 간섭을 최소화한 플래시 메모리용 센스 앰프 설계)

  • Kim, Byong-Rok;So, Kyoung-Rok;You, Young-Gab;Kim, Sung-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.6
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    • pp.1-8
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    • 2000
  • In this paper, design of sense amplifier for a flash memory minimizing bit line disturbance due to common bit line is presented. There is a disturbance problem at output modes by using common bit line, when the external devices access an internal flash memory. This phenomenon is resulted form hot carrier between floating gates and bit lines by thin oxide thickness. To minimize bit line disturbance, lower it line voltage is required and need sense amplifier to detect data existence in lower bit line voltage. Proposed circuits is operated at lower bit line voltage and we fabricated a embedded flash memory MCU using 0.6u technology.

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A Real-Time JPEG2000 Codec Implementation on ARM9 Processor (ARM9 프로세서용 실시간 JPEG2000 코덱의 구현)

  • Kim, Young-Tae;Cho, Shi-Won;Lee, Dong-Wook
    • Journal of the Institute of Convergence Signal Processing
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    • v.8 no.3
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    • pp.149-155
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    • 2007
  • In this paper, we propose an real-time implementation of JPEG2000 codec on the ARM9 processor. The implemented codec is designed to separate control codes from data management codes in order to use effectively the system resources such as processor and memory. Especially, in embedded situations like cellular phones it is very important to provide good services using limited processor and internal memory. Since ARM9 series processors do not provide floating-point, large amount of computational time is required to perform the operation which needs highly repetitive floating-point computations like DWT(discrete wavelet transform). The proposed codec was programed using fixed-point to overcome this weakness. Also code optimization considering cache memory was applied to further improve the computational speed.

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