• 전기전자학회논문지
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• 제14권3호
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• pp.250-255
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• 2010

본 논문에서는 DTMOS(Dynamic Threshold voltage MOSFET) 스위칭 소자를 사용한 인터리브 방식의 전원제어 장치(PMIC)를 제안하였다. 휴대기기에 필요한 높은 출력 전압과 낮은 출력 전압을 제공하기 위하여 벅-부스트 컨버터를 사용하였다. 또한, 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하였다. 낮은 온-저항을 갖는 DTMOS를 사용하여 도통 손실을 감소시켰으며 인터리브 방식을 사용하여 출력 리플을 감소시켰다. 1mA 이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

• Journal of Power Electronics
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• 제12권3호
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Journal of Power Electronics
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• 제14권4호
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• pp.661-670
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• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• 전력전자학회논문지
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• 제20권1호
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• pp.65-71
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• 2015

This paper presents the efficiency analysis of a critical current mode interleaved PFC rectifier, in which each of three different semiconductor switches is employed as the active switch. The Si FET, SiC FET, and GaN FET are consecutively used with the prototype PFC rectifier, and the efficiency of the PFC rectifier with each different semiconductor switch is analyzed. An equivalent circuit model of the PFC rectifier, which incorporates all the internal losses of the PFC rectifier, is developed. The rms values of the current waveforms main circuit components are calculated. By adapting the rms current waveforms to the equivalent model, all the losses are broken down and individually analyzed to assess the conduction loss, switching loss, and magnetic loss in the PFC rectifier. This study revealed that the GaN FET offers the highest overall efficiency with the least loss among the three switching devices. The GaN FET yields 96% efficiency at 90 V input and 97.6% efficiency at 240 V, under full load condition. This paper also confirmed that the efficiency of the three switching devices largely depends on the turn-on resistance and parasitic capacitance of the respective switching devices.

• 전력전자학회논문지
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• 제21권2호
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• pp.95-101
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• 2016

This paper proposed a high-power density bidirectional converter for hybrid electric vehicle high-voltage DC-DC converter(HDC). The conventional HDC has two disadvantages. First, large inductance is required to satisfy the ripple current of inductor by low switching frequency (<20 kHz). Second, large core size is required to prevent the saturation of inductor by high current. Compared with the conventional HDC, the proposed HDC can reduce inductance with SiC-FET for high frequency driving. High-power density of I/O capacitors can be achieved through two-phase interleaved method. The high-power density of inductors can be achieved because the offset current of magnetizing inductance is theoretically terminated by using the differential mode coupled inductor instead of using two single inductors. The validity of the proposed converter is proved through the 50 kW prototype.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.330-331
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• 2011

The interleaving method is usually used to reduce the ripple of output current of filter inductor in parallel operation of PWM DC/DC converter. Although the current ripple of filter inductor decreases, each current ripple of filter inductor is not decreased. In this study, the operation of interleaved buck converter with coupled inductor is analyzed in each operation mode. It is verified through experiment. The possibility of application to grid connected inverter with parallel operation is identified.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.547-550
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• 2004

An interleaved single-stage power-factor-correction (PFC) AC/DC converter is presented in this paper. The proposed converter is combined by two single-stage AC/DC converters based on flyback converter Each PFC stage operates in discontinuous conduction mode (DCM). By exploiting the interleaving technique, the input ripple current and output ripple voltage are reduced. The proposed converter complied with EN/1EC61000-3-2 harmonic regulations achieves high efficiency and low cost. The performance of the proposed converter was evaluated on a 180W $(90W\times2,\;24V,\;7.5A)$ experimental prototype.

• Journal of Power Electronics
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• 제16권5호
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• pp.1735-1742
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• 2016

This paper proposes an interleaved five-level boost converter based on a switched-capacitor network. The operating principle of the converter under the CCM mode is analyzed. A high voltage gain, low component stress, small input current ripple, and self-balancing function for the capacitor voltages in the switched-capacitor networks are achieved. In addition, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop has been researched to achieve good performances and voltage-balance effect. An experimental study has been done to verify the correctness and feasibility of the proposed converter and control strategy.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 춘계학술대회 논문집 에너지변화시스템부문
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• pp.152-155
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• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• 반도체디스플레이기술학회지
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• 제17권1호
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• pp.21-26
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• 2018

In this paper, a multiple coupling inductor with expandable-integrated magnetic structure was proposed to enable miniaturization of external switched mode power supply (SMPS) for a large display. Inductance formula of the proposed inductor structure was derived through magnetic circuit analysis for a simple inductance designing process. The proposed inductor was applied into a 1kW class interleaved bridgeless power factor correction circuit which requires four inductors, and experimental steady state result of the circuit was compared. According to the experimental result, it was found that the proposed multiple coupling inductor shows the electrical characteristics that can replace the conventional separated inductors and is suitable for miniaturization of the SMPS since the circuit configuration is possible with one shared inductor.