• Journal of the Korean Magnetics Society
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• v.17 no.4
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• pp.147-151
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• 2007

We have investigated the half-metallicity and magnetism for the Heusler ferromagnet $Co_2$ZrSi interfaced with semiconductor ZnTe along the (001) plane by using the full-potential linearized augmented plane wave (FLAPW) method. We considered low types of possible interfaces: ZrSi/Zn, ZrSi/Te, Co/Zn, and Co/Te, respectively. From the calculated density of states, it was found that the half-metallicity was lost at all the interfaces, however for the Co/Te system the value of minority spin density of states was close to zero at the Fermi level. These facts are due to the interface states, appeared in the minority spin gap in bulk $Co_2$ZrSi, caused by the changes of the coordination and symmetry and the hybridizations between the interface atoms. At the Co/Te interface, the magnetic moments of Co atoms are 0.68 and $0.78{\mu}_B$ for the "bridge" and "antibridge" sites, respectively, which are much reduced with respect to that ($1.15{\mu}_B$) of the bulk $Co_2$ZrSi. In the case of Co/Zn, Co atoms at the "bridge" and "antibridge" sites have magnetic moments of 1.16 and $0.93{\mu}_B$, respectively, which are almost same or slightly decreased compared to that of the bulk $Co_2$ZrSi. On the other hand, for the ZrSi/Zn and ZrSi/Te systems, the magnetic moments of Co atoms at the sub-interface layers are in the range of $1.13{\sim}1.30\;{\mu}_B$, which are almost same or slightly increased than that of the bulk $Co_2$ZrSi.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.23-30
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• 1997

For a effective management and easy tool integration of CAD database, Hierarchy interface System(HIS) was designed and GROCO(Graph Representation fOr Complex Objects) Model was presented in another my paper[10]. Hierarchy Interface System which is composed of two subsystems of a configurator and a converter is designed for the interface between a conventional database management system and CAD tools. In this paper, Version Management System is presented for supporting effective operations of HIS using GROCO model. Version Management System supports efficiently CAD database charaters having a hierarchical structure of composite objects. In Version Management System, A design evolves in discrete states through mutation and derivation for going phases of design giving rise to multiple versions. Operations and rules are provided transition between their different states. and for controlling update propagation and preventing version proliferation. Version Modeling Graph is proposed for dealing with versioning at the instance and type levels.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.644-647
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• 2001

The investigations were discussed on the radiation effects of the electrical properties to the p-type MOS capacitors, which were irradiated by cobalt-60 gamma ray sources. The characteristics of capacitance-bias voltage(C-V) and of dielectric dissipation tarter-bias voltage(D-V) on the capacitors were measured at 1 [MHz] frequency. The microscopic behaviors of spate charges in oxide and silicon-silicon dioxide(Si- $SiO_2$) interface were investigated from the experimental data. The C-V characteristics are statical and convenient for the evaluation of the steady state behavior of carriers and interface states characteristics. While, the distribution and magnitude of space charges in oxide can be found out accurately on the $V_{dp}$ in D-V curves. The density of interface states can be deduced with ease from the magnitude of D-peak at depletion state. Thus, it is also concluded that the D-V curves are more useful and easier than conventional C-V curves for analysis of the microscopic and dynamic behavior of carriers in oxide and Si- $SiO_2$interface.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.122-129
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• 1995

The most important feature of a-Si TFT is dense localized states such as dangling bonds which exist in tis bandgap. Electrons trapped by localized states dominate the potential distribution in the active a-Si region ,and influence the performance of a-Si TFT. In this paper, we describe the electrical characteristics of a-Si TFT with respect to trap distribution within bandgap, electron mobility and interface states using 2-Dimensional device simulator and compare the result of simulation with measurements. Using the mixed-mode simulator, we can predict the potential variation of pixel which causes residual image problem during the turn-off of a-Si TFT driving circuit. Therefore it is possible to consider trade-off between potential variation of pixel and turn-on current of a-Si TFT for the optimized driving circuit.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.11-17
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• 1998

Although GaAs HBTs are very attractive for high power amplifier because of their power handling capablity, they can't be actively commercialized due to the degradation of current gain occured in hihg current operation. In this paper we analyzed the type of current gain degradation of GaAs HBTs under high constant current stress, and identified the mechanism by using two dimensional numerical simulation. The cause of degradation was found out to be the variation of surface recombination states at the interface between GaAs extrinstic base and the nitride passivating the surface of base. The energy radiated from recombination of carriers in bulk as well as near the surface is estimated to activate the change of the surface states.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.212-212
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• 2009

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• Journal of the Korean Magnetics Society
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• v.5 no.5
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• pp.442-446
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• 1995

Electronic structures of Fe overlayers on Cr(Fe/Cr) films, with an Fe coverage of $1-20{\AA}$, have been investigated by using photoemission spectroscopy. Experimental results are compared with supercell band structure calculations for a system with monolayer (ML) Fe on each side of five layer Cr, Fe(1ML)/Cr(5ML)/Fe(1ML). The extracted Fe 3d partial spectral weight in Fe/Cr exhibits very interesting features for very thin Fe overlayers. First, a sharp emissionnear the Fermi energy is observed, which is expected to originate primarily from hybridization between Fe and Cr 3d electrons at the Fe/Cr interface, and partially from the Fe 3d surface states in the Fe overlayer. Second, other structures are observed at higher binding energies which resemble the Cr 3d valence bands, also suggesting large hybridization between Fe and Cr 3d states at the Fe/Cr interface. These conjectures are confirmed by band structure calculations for Fe(1ML)/Cr(5ML)/Fe(1ML).

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.