• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.143.1-143.1
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• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• 한국세라믹학회지
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• 제26권5호
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• pp.661-669
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• 1989

The defect structure in LiNbO3 single crystals grown by Czochralski method from the congruently melting composition were investigated. Chemical etching patterns were studied in x-plane, z-plane, and major cleavage plane, respectively, dislocation density was higher at the periphery of crystals than at the center because the thermal stress due to radial temperature gradient had a main effect on it, as compared with dislocations formed from the solid-liquid interface. Many dislocation lineages were arranged along several directions.

• 한국전기전자재료학회논문지
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• 제27권10호
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• pp.648-652
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• 2014

We have investigated the effect of electrical properties of amorphous InGaZnO thin film transistors (a-IGZO TFTs) by post thermal annealing in $O_2$ ambient. The post-annealed in $O_2$ ambient a-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has better performance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well as reasonable threshold voltage, than others do. The interface trap density is controlled to achieve the optimum value of TFT transfer and output characteristics. The device performance is significantly affected by adjusting the annealing condition. This effect is closely related with the modulation annealing method by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.103.1-103.1
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• 2011

실리콘 이종접합 태양전지에서 계면 결함 밀도는 효율을 결정하는데 가장 중요한 요인으로 작용한다. 계면 결함은 캐리어의 재결합 위치로 작용하여, 계면 결함 밀도가 증가하면 재결합 속도가 증가하게 된다. 흡수층으로 사용되는 실리콘 웨이퍼 (결정질 실리콘)를 가능한 깨끗하게 세정함으로써, 또한 emitter로 쓰이는 비정질 실리콘을 낮은 데미지로 증착하여 계면 결함 밀도를 감소 시킬 수 있다. 이러한 계면 결함 밀도의 감소가 어떠한 변화로 인해 태양전지 특성에 영향을 주는지 시물레이션을 통해 알아보았다. n-type 웨이퍼에 p-type 비정질 실리콘을 emitter로 하여 TCO/p/i/n-type wafer/i/n/TCO/metal의 구조를 적용했고, wafer 전면과 i로 쓰인 무첨가된 비정질 실리콘 간의 계면 결함 밀도를 변수로 적용했다. 그 결과, 계면 결함 밀도가 감소함에 따라 재결합이 감소하여 태양전지 특성이 증가하는 측면도 있지만, 흡수층의 장벽 (barrier height)이 높아져 재결합을 더욱 감소시킴으로 인해 태양전지 특성이 증가함을 알 수 있었다.

• Applied Science and Convergence Technology
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• 제26권5호
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• 전기전자학회논문지
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• 제26권1호
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• pp.50-55
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• 2022

SiC는 차세대 전력반도체의 핵심 재료로 넓은 밴드갭과 높은 절연파괴강도, 열전도율을 가지고 있지만 deep level defect와 같은 다양한 문제를 야기하는 결함이 존재한다. SiC에서 나타나는 defect는 물성에서 나타나는 defect와 계면에서 나타나는 interface trap 2가지로 나뉜다. 본 논문은 상온 (300 K)에서 보고되는 Z_1/2 trap concentration 0 ~ 9×10¹⁴ cm^-3을 SiC substrate와 epi layer에 적용하여 turn-on 특성을 알아보고자 한다. 전류밀도와 SRH(Shockley-Read-Hall), Auger recombination을 통해 구조 내 재 결합률을 확인하였다. trap concentration이 증가할수록 turn-on시 전류밀도와 재 결합률은 감소하며 Ron은 0.004에서 0.022 mΩ으로 약 550% 증가하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• 한국결정성장학회지
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• 제12권6호
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• pp.299-303
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• 2002

The relationship of crystallinity between defects distribution with (100) ZnTe/GaAs using HWE growth was investigated by four crystal rocking curve (FCRC) and transmission electron microscopy (TEM). The thickness dependence of crystal quality in ZnTe epilayer was evaluated. The FWHM value shows a strong dependence on ZnTe epilayer thickness. For the films thinner than 6 ${\mu}{\textrm}{m}$, the FWHM value decreases very steeply as the thickness increases. For the films thicker than 6 ${\mu}{\textrm}{m}$, it becomes an almost constant value. At the thickness of 12 $\mu\textrm{m}$ with the smallest value of 66 arcsec. which is the best value so far reported on ZnTe epilayers was obtained. Investigation into the nature and behavior of dislocations with film thickness in (100) ZnTe/(100)GaAs heterostructures grown by Hot Wall Epitaxy (HWE). This film defects range from interface to 0.7 ${\mu}{\textrm}{m}$ thickness was high density, due to the large lattice mismatch and thermal expansion coefficients. The thickness of 0.7~1.8 ${\mu}{\textrm}{m}$ was exists low defect density. In the thicker range than 1.8 ${\mu}{\textrm}{m}$ thickness was measured hardly defects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.140-143
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• 2003

BST thin films have a good thermal-chemical stability, insulating effect and variety of phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the structural characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• 한국전기전자재료학회논문지
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• 제27권9호
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• pp.547-550
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• 2014

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/$SiO_2$ structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage ($V_{FB}$) shift was positive. Near-interface trap charge density ($N_{it}$) and negative oxide trap charge density ($N_{ox}$) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.