• 제목/요약/키워드: interface charge

검색결과 470건 처리시간 0.024초

Use of Inner Ionomer Solution in Preparing Membrane-Electrode Assembly (MEA) for Fuel Cells and Its Characterization

  • Seo, Seok-Jun;Woo, Jung-Je;Yun, Sung-Hyun;Park, Jin-Soo;Moon, Seung-Hyeon
    • Korean Membrane Journal
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    • 제10권1호
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    • pp.46-52
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    • 2008
  • Optimization of ionomer solution was conducted in order to improve the performance of MEAs in PEMPC. The interface between membrane and electrodes in MEAs is crucial region determining fuel cell performance as well as ORR reaction at cathode. Through the modification of Nafion ionomer content at the interface between membrane and electrodes, an optimal content was obtained with Nafion 115 membranes. Two times higher current density was obtained with the outer Nafion sprayed MEA compared with the non-sprayed one. In addition, the symmetrical impedance spectroscopy mode (SM) exhibited that the resistances of membrane area, proton hydration, and charge transfer decreased as the outer Nafion is sprayed. From the polarization curves and SM, the highest current density and the lowest resistance was obtained at the outer ionomer content of $0.15\;mg\;cm^{-2}$.

도시철도의 열차출입문제어에 관한 연구 (A Case Study for SMRT Train Open Doors Control System)

  • 원유덕;심원섭
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2006년도 추계학술대회 논문집
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    • pp.941-946
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    • 2006
  • It followed in system development and SMRT(Seoul Metropolitan Rapid Transit Co)System reached to an automatic train operation(ATO) and driverless operation(DLM) from the manual operation due to the train driver. The train like the general bus or the car vehicle was not serial riding in a car and the Parallel concept which the numerous passenger rides in a car simultaneously occur frequently the charge of the train driver unmanned bitterly from existing manual handling was a possibility of doing, train open door control(ODM) which bites also ATO, it handles it minimized. Like this ATO/DLM, the control system which bites being a Wayside to Train communication for immediacy, it is a system of the Vital concept the immediacy of the citizen Data evil the radio information transmission and the train of the interface which is accurate from unmanned operation and, will decipher, will accomplish it will guarantee. It respects the passenger accident prevention and an air question environment improvement from subway platform and phul leys the screen door of Platform(PSD) with the fire tube frost it refers and part it treats and to sleep it does, ODM which bites is accuracy and immediacy of altitude and when seeing from the viewpoint which demands the trust of altitude, ODM system the trust of car incest interface in the equipment construction which is safe and the comparative analysis back of the system analysis against the control which bites and case study and other subway system it leads from the research which it sees and signal - train in base grudge to sleep it contributes it does.

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박막트랜지스터 응용을 위한 SiO2 박막 특성 연구 (Studies for Improvement in SiO2 Film Property for Thin Film Transistor)

  • 서창기;심명석;이준신
    • 한국전기전자재료학회논문지
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    • 제17권6호
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    • pp.580-585
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    • 2004
  • Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

정보 시스템을 이용한 항공기 착륙요율 결정 사례 연구;잔액 보상 방식에 의한 착륙요율 결정 방법 중심 (A Case Study on the Decision of Aircraft Landing Charge Utilizing Information Technology)

  • 유광의;김봉균
    • 한국항공운항학회지
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    • 제6권1호
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    • pp.147-163
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    • 1998
  • The purpose of this research is to look for the best description of calculating the reasonable Landing Fee. Landing Fee is consisted one of major revenues for maintaining an airport. Traditional Landing Fee Rate has been charged based on the weight factor; Maximum take-off weight, Maximum landing weight, or Maximum authorized weight. To achieve a better reliable value of Landing Fee Rate, The elements of Noise and Peak-Time have to be considered as well as the aircraft weight. This research designs the algorithms for calculating Landing Fee Rate and also Landing Fee, based on the aircraft weight. The Network is also applied to above. That is, CGI(Common Gate Interface) is constructed to interface the terminal of calculating Landing Fee Rate, and the terminal of collecting and transmitting the data such as the Weight. The computer language on the CGI was made by C++ and PERL. The main point of this research is to integrate the airport and Information System and to construct the database which is based on the different perspective of calculating Landing Fee Rate. However, the result of the most efficient and reliable will be computed based on above. This research will broaden the range of application up to the each case of airports.

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65 nm CMOS 기술에서 소자 종류에 따른 신뢰성 특성 분석 (Analysis of Reliability for Different Device Type in 65 nm CMOS Technology)

  • 김창수;권성규;유재남;오선호;장성용;이희덕
    • 한국전기전자재료학회논문지
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    • 제27권12호
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    • pp.792-796
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    • 2014
  • In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

Application of the Runge Kutta Discontinuous Galerkin-Direct Ghost Fluid Method to internal explosion inside a water-filled tube

  • Park, Jinwon
    • International Journal of Naval Architecture and Ocean Engineering
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    • 제11권1호
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    • pp.572-583
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    • 2019
  • This paper aims to assess the applicability of the Runge Kutta Discontinuous Galerkin-Direct Ghost Fluid Method to the internal explosion inside a water-filled tube, which previously was studied by many researchers in separate works. Once the explosive charge located at the inner center of the water-filled tube explodes, the tube wall is subjected to an extremely high intensity fluid loading and deformed. The deformation causes a modification of the field of fluid flow in the region near the water-structure interface so that has substantial influence on the response of the structure. To connect the structure and the fluid, valid data exchanges along the interface are essential. Classical fluid structure interaction simulations usually employ a matched meshing scheme which discretizes the fluid and structure domains using a single mesh density. The computational cost of fluid structure interaction simulations is usually governed by the structure because the size of time step may be determined by the density of structure mesh. The finer mesh density, the better solution, but more expensive computational cost. To reduce such computational cost, a non-matched meshing scheme which allows for different mesh densities is employed. The coupled numerical approach of this paper has fewer difficulties in the implementation and computation, compared to gas dynamics based approach which requires complicated analytical manipulations. It can also be applied to wider compressible, inviscid fluid flow analyses often found in underwater explosion events.

수열합성 공정으로 합성된 산화갈륨의 상변화에 따른 광촉매 특성 (Photocatalytic Properties of Hydrothermally Synthesized Gallium Oxides at Different Phase Polymorphs)

  • 류희중;김선재;이인규;오훈정;황완식
    • 반도체디스플레이기술학회지
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    • 제20권2호
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    • pp.98-102
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    • 2021
  • GaOOH is obtained via hydrothermal synthesis procedure. The formed GaOOH is turned into α-Ga2O3 at 500℃ annealing. As the annealing temperatures increase the α-Ga2O3 is in part turned into β-Ga2O3 and fully turned into β-Ga2O3 after 1100℃. XPS and PL results reveal that heterojunction interface between α-Ga2O3 and β-Ga2O3 become maxim at 500℃ annealing condition, which result in the highest photocatalytic activity. The presence of heterojunction interface slows down the recombination process by separating photogenerated electron-hole pairs and thereby enhance the overall photocatalytic activity.

주석-납 기반 페로브스카이트 고농도 전구체 용액을 이용한 광전류 향상 연구 (Study for Improved Photocurrent via High Concentrated Tin-lead Perovskite Precursor Solution)

  • 홍효진;이승민;임정민;노준홍
    • Current Photovoltaic Research
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    • 제11권3호
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    • pp.96-102
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    • 2023
  • Sn-Pb narrow-bandgap perovskite solar cells, which is a light-harvesting layer thicker than 1.3 micrometers, is needed to enhance the low photocurrent. The fabrication of such a thick film through solution processing is a key challenge. Here, we studied and characterized the film by using a precursor solution of increased concentration, comparing it with the universally used 1-micrometer Sn-Pb perovskite film. The increase in molar concentration clearly induced thickness enhancement, but we observed that it also created numerous voids at the interface with bottom charge transporting layer. We hypothesized that these voids might hinder the increase in photocurrent associated with thickness enhancement. By introducing methylammonium chloride (MACl), we successfully fabricated Sn-Pb perovskite film with a thickness of 1.3 micrometer and no voids. Void-controlled Sn-Pb perovskite solar cells not only demonstrated superior short-circuit current density compared to those with voids but also operated smoothly under light exposure.

First-principles investigations on helium behaviors in oxide-dispersion- strengthened nickel alloys with Hf additions

  • Yiren Wang;Fan Jia;Yong Jiang
    • Nuclear Engineering and Technology
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    • 제55권3호
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    • pp.895-901
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    • 2023
  • Oxide-dispersion- strengthened nickel alloys with Hf additions are expected to present high temperature mechanical properties and durable helium resistance based on first-principles density functional theory (DFT) calculations. Energetic and charge density evaluations of the helium behaviors were performed in Ni matrix, Y2Hf2O7 oxide and the oxide/matrix interface. With the presence of coherent Y2Hf2O7 in Ni matrix, chances of helium bubbles in Ni can be greatly diminished. The helium atoms shall occupy the interfacial site initially, then diffuse into in the octahedral sites of Y2Hf2O7, and these oxide-captured He atoms prefer to separate individually. Much higher diffusion barrier of He in Y2Hf2O7 than in nickel is related to the strong hybridization between interstitial He-1s and nearest-neighboring O-2p orbitals.

UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계 (A design on low-power and small-area EEPROM for UHF RFID tag chips)

  • 백승면;이재형;송성영;김종희;박문훈;하판봉;김영희
    • 한국정보통신학회논문지
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    • 제11권12호
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    • pp.2366-2373
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    • 2007
  • 본 논문에서는 $0.18{\mu}m$의 EEPROM cell을 사용하여 수동형 UHF RFID 태그 칩에 사용되는 저전력, 저면적의 1Kbits 비동기식 EEPROM IP를 설계하였다. 저면적 회로 설계 기술로는 $0.18{\mu}m$ EEPROM 공정을 이용하여 비동기식 EEPROM IP를 설계하므로 command buffer와 address buffer를 제거하였고 separate I/O 방식을 사용하므로 tri-state 데이터 출력 버퍼(data output buffer)를 제거하였다. 그리고 저전압(low voltage)의 VDD에서 EEPROM cell이 필요로 하는 고전압(high voltage)인 VPP와 VPPL 전압을 안정적으로 공급하기 위해 기존의 PN 접합 다이오드 대신 Schottky 다이오드를 사용한 Dickson 전하펌프를 설계하므로 전하펌프의 펌핑단(pumping stage)의 수를 줄여 전하펌프가 차지하는 면적을 줄였다. 저전력 회로 설계 기술로 Dickson 전하 펌프(charge pump)를 이용하여 VPP generator를 만들고 Dickson 전하펌프의 임의의 노드 전압을 이용하여 프로그램과 지우기 모드에서 각각 필요로 하는 VPPL 전압을 선택하도록 하게 해주는 VPPL 전원 스위칭 회로를 제안하여 쓰기전류(write current)를 줄이므로 저전력 EEPROM IP를 구현하였다. $0.18{\mu}m$ 공정을 이용하여 설계된 비동기식 EEPROM용 테스트 칩은 제작 중에 있으며, 비동기식 1Kbits EEPROM의 레이아웃 면적은 $554.8{\times}306.9{\mu}m2$로 동기식 1Kbits EEPROM에 비해 레이아웃면적을 11% 정도 줄였다.