• 제목/요약/키워드: interface charge

검색결과 470건 처리시간 0.027초

Nano CMOSFET에서 Channel Stress가 소자에 미치는 영향 분석 (Characterization of the Dependence of the Device on the Channel Stress for Nano-scale CMOSFETs)

  • 한인식;지희환;김경민;주한수;박성형;김용구;왕진석;이희덕
    • 대한전자공학회논문지SD
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    • 제43권3호
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    • pp.1-8
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    • 2006
  • 본 논문에서는 채널 stress에 따른 Nano-scale CMOSFET의 소자 및 신뢰성 (HCI, NBTI)특성을 분석하였다. 잘 알려져 있듯이 NMOS는 tensile, PMOS는 compressive stress가 인가된 경우에 소자의 특성이 개선되었으며, 이는 전자와 정공의 이동도 증가에 의한 것임을 확인하였다. 그러나 신뢰성인 경우에는 소자 특성과는 다른 특성을 나타냈는데, NMOS와 PMOS 모두 tensile stress가 인가된 경우에 hot carrier 특성이 더 열화 되었으며, PMOS의 PBTI 특성도 tensile에서 더 열화 되었음을 확인하였다. 신뢰성을 분석한 결과, 채널의 tensile stress로 인하여 $Si/SiO_2$ 계면에서 interface trap charge의 생성과 산화막 내 positive fixed charge의 생성에 많은 영향을 끼침을 알 수 있었다. 그러므로 나노급 CMOSFET에 적용되는 strained-silicon MOSFET의 개발을 위해서는 소자의 성능 뿐 만 아니라 신뢰성 또한 고려되어야 한다.

유기반도체와 절연체 계면제어를 통한 유기전하변조 트랜지스터의 전기적 특성 향상 연구 (Tuning Electrical Performances of Organic Charge Modulated Field-Effect Transistors Using Semiconductor/Dielectric Interfacial Controls)

  • 박은영;오승택;이화성
    • 접착 및 계면
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    • 제23권2호
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    • pp.53-58
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    • 2022
  • 본 연구는 AlOx유전체 표면에 유기 자립조립 단분자막 (self-assembled monolayer, SAM) 중간층을 도입함으로써 유전체의 표면특성을 제어하고, 최종적으로 유기전하변조트랜지스터 (Organic charge modulated field-effect transistor, OCMFET)의 전기적 특성을 향상시킨 결과를 제시하였다. 유기 중간층을 적용함으로써, OCMFET의 컨트롤 게이트(CG, Control gate)와 플로팅 게이트 (FG, Floating gate) 사이 커패시터 플레이트로 작용하는 산화알루미늄 게이트 유전체의 표면 에너지를 제어하였으며, FET의 가장 중요한 성능변수인 전계효과 이동도(field-effect transistor, μFET)를 향상시켰다. 사용된 SAMs은 네가지의 PA (Octadecylphosphonic acid, Butylphosphonic acid, (3-Bromopropyl)phosphonic acid, (3-Aminopropyl) phosphonic acid)를 사용하여 형성하였으며, 각각 0.73, 0.41, 0.34, 0.15 cm2V-1s-1의 μOCMFET를 나타내었다. 이 연구를 통해 유기 SAM 중간층의 알킬 체인(Alkyl chain)의 길이 및 말단기의 특성이 소자의 전기적 성능을 제어하는데 중요한 요인임을 확인하였으며, 이 결과를 통해 향후 최적의 센서 플랫폼으로서의 OCMFET 소자성능 최적화에 기여할 수 있을 것으로 기대한다.

도포된 오일의 변화에 따른 Epoxy/EPDM 계면의 교류 절연 파괴 특성에 관한 연구 (A Study on the AC Interfacial Breakdown Properities of the Interface between Epoxy/EPDM with the variation of spreaded oil)

  • 배덕권;이수길;정일형;이준웅
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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    • pp.897-899
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    • 1999
  • In this paper, the interfacial dielectric breakdown phenomenon of interface between Epoxy/EPDM (ethylene propylene diene terpolymer) was discussed, which affects stability of insulation system of power delivery devices. Specimen structure was designed by using MAGSOFT's FLUX2D based on the finite elements method. Design concepts is to reduce the effect of charge transport from electrode in the process of breakdown and to have the tangential electrical potential with the Epoxy/EPDM interface. AC interfacial breakdown phenomenon of was investigated by variation of interfacial conditions oil and temperature which are supposed to have influence on the interfacial breakdown strength. Interfacial breakdown strength was improved by spreading oil over interfacial surface. The decreasing ratio of the AC interfacial breakdown strength in non-oiled specimens was increased by the temperature rising and its of oiled specimens was not affected by temperature.

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Development of Simple Solvent Treating Methods to Enhance the Efficiency of Small-Molecule Organic Solar Cells

  • Kim, Jin-Hyun;Heo, Il-Su;Gong, Hye-Jin;Yu, Yeon-Gyu;Yim, Sang-Gyu
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.276-276
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    • 2012
  • The interface morphology of organic active layers is known to play a crucial role in the performance of organic photovoltaic (OPV) cells. Especially, a controlled nanostructure with a large contact area between electron donor (D) and acceptor (A) layers is necessary to improve the power conversion efficiency (PCE) of the cells since the short exciton diffusion lengths in organic semiconductors limit the charge (hole and electron) separation before excitons recombination. In this work, we developed simple solvent treating methods to fabricate a nanostructured DA interface and applied them to enhance the PCE of ZnPc/C60 based small molecule OPV cells. Interestingly, it was observed that the solvent treatment on the donor layer prior to the deposition of the acceptor layer resulted in a significant decrease in PCE, which was due to an existence of undesirable voids at the DA interface. Instead, the solvent vapor treatment after the DA bilayer formation led to densely packed and well dispersed DA contacts. Consequently, 3-fold enhancement of PCE as compared to the untreated bilayer cell was accomplished.

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Improving Interface Characteristics of Al2O3-Based Metal-Insulator-Semiconductor(MIS) Diodes Using H2O Prepulse Treatment by Atomic Layer Deposition

  • Kim, Hogyoung;Kim, Min Soo;Ryu, Sung Yeon;Choi, Byung Joon
    • 한국재료학회지
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    • 제27권7호
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    • pp.364-368
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    • 2017
  • We performed temperature dependent current-voltage (I-V) measurements to characterize the electrical properties of $Au/Al_2O_3/n-Ge$ metal-insulator-semiconductor (MIS) diodes prepared with and without $H_2O$ prepulse treatment by atomic layer deposition (ALD). By considering the thickness of the $Al_2O_3$ interlayer, the barrier height for the treated sample was found to be 0.61 eV, similar to those of Au/n-Ge Schottky diodes. The thermionic emission (TE) model with barrier inhomogeneity explained the final state of the treated sample well. Compared to the untreated sample, the treated sample was found to have improved diode characteristics for both forward and reverse bias conditions. These results were associated with the reduction of charge trapping and interface states near the $Ge/Al_2O_3$ interface.

SONOSFET EEPROM웨 열화에 따른 Si-SiO$_2$ 계면특성 조사 (Investigation on Si-SiO$_2$ Interface Characteristics with the Degradation in SONOSFET EEPROM)

  • 이상은;김선주;이성배;이상배;서광열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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    • pp.116-119
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    • 1994
  • The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

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Study of Self-assembled Organic Layer Formation at the HATCN/Au Interface

  • Kim, Ji-Hoon;Won, Sangyeon;Kwon, Young-Kyun;Kahng, Se-Jong;Park, Yongsup
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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    • pp.150.2-150.2
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    • 2013
  • We elucidate the mechanism of the self-assembled organic layer formation at the organic/metal interface of hexaaza-triphenylene-hexacarbonitrile (HATCN)/Au(111) by first-principles calculations and Lowtemperature scanning tunneling microscope (STM). In this work, we used HATCN to deposit organic material which is well known as an efficient OLED charge generation material. Low-temperature STM measurements revealed that self-assembled hexagonal porous structure is formed at terraces of Au(111). We also found that the hexagonal porous structure has chirality and forms only small (<1000 $nm^2$) phaseseparated chiral domains that can easily change their chiral phase in subsequence STM images at 80 K. To explain the mechanism of these observation, we calculated the molecular-molecular and molecule-surface interaction energies by using density functional theory method. We found that the change of their chiral phase resulted from the competition between the two energies. These results have not only verified our experimental observations, but also revealed the delicate balance between different interactions that caused the self-assembed structures at the surface.

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Modification of Schottky Barrier Properties of Ti/p-type InP Schottky Diode by Polyaniline (PANI) Organic Interlayer

  • Reddy, P.R. Sekhar;Janardhanam, V.;Jyothi, I.;Yuk, Shim-Hoon;Reddy, V. Rajagopal;Jeong, Jae-Chan;Lee, Sung-Nam;Choi, Chel-Jong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권5호
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    • pp.664-674
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    • 2016
  • The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

복합산화물 $(Ba Ca)TiO_3$-ZnO의 구조적 및 유전분극 특성 (The structural and dielectric polarization characteristics of composite oxide material in $(Ba Ca)TiO_3$-Zn)

  • 홍경진;임장섭;정우성;민용기;김용주;김태성
    • E2M - 전기 전자와 첨단 소재
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    • 제10권3호
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    • pp.239-246
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    • 1997
  • The ZnO is stabilize dielectric constant over a broad temperature range because its addition makes the relaxation time short. In this study, the composite oxide material (B $a_{0.85}$ $Ca_{0.15}$)Ti $O_{3}$ was mixed by ZnO additive material and the dielectric polarization characteristics was studied. The relative density was over 90[%] at all specimen in the structural characteristics. Among of the specimen, the relative density of (B $a_{0.85}$ $Ca_{0.15}$)Ti $O_{3}$ with ZnO (0.4mol) has a 95[%]. The grain size of composite oxide material with an increasing ZnO increased and it was 1.0[.mu.m]-1.22[.mu.m]. In the electrical characteristics, the charge and discharge current was increased by ZnO addition. The dielectric relaxation time was increased by space charge polarization at above 110[.deg. C] and the dielectric relaxation time was fixed by space charge polarization of para-dielectric layer at below 110[.deg. C]. The dielectric relaxation time was maximum when the grain size was small. The dielectric relaxation time is decreased with an additive material ZnO and interface polarization, existing void at the grain and grain boundary. The remnant polarization is increased and the coercive electric field is decreased by ZnO.

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주입 전하량의 실시간 제어에 의한 PPLN 제작 및 분극반전 과정 분석 (Fabrication of PPLN by Real-Time Control of a Transferred Charge and Analysis of Domain Inversion Process)

  • 권재영;김현덕;송재원
    • 한국광학회지
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    • 제17권3호
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    • pp.262-267
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    • 2006
  • 효율적인 PPLN 제작을 위하여 DC 전계를 인가하면서 $LiNbO_3$에 인가되는 전압 및 전류를 실시간으로 측정할 수 있는 실험 장치를 제안하였다. 제안된 실험 장치를 사용함으로써 PPLN의 분극반전에 필요한 충분한 전하량을 공급하기 위한 전계인가시간을 수초 단위로 증가시킬 수 있어 $LiNbO_3$에 주입되는 전하량의 조절을 용이하게 할 수 있었다. 또한 PPLN의 분극반전 과정을 단계별로 분류하고 각 단계별 실험결과를 바탕으로 분석함으로써 최적의 PPLN 제작조건을 구할 수 있었다.