• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• Journal of Adhesion and Interface
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• v.23 no.2
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• pp.53-58
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• 2022

Here, the surface characteristics of the dielectric were controlled by introducing the self-assembled monolayers (SAMs) as the intermediate layers on the surface of the AlOx dielectric, and the electrical performances of the organic charge modulated transistor (OCMFET) were significantly improved. The organic intermediate layer was applied to control the surface energy of the AlOx gate dielectric acting as a capacitor plate between the control gate (CG) and the floating gate (FG). By applying the intermediate layers on the gate dielectric surface, and the field-effect mobility (μ_OCMFET) of the OCMFET devices could be efficiently controlled. We used the four kinds of SAM materials, octadecylphosphonic acid (ODPA), butylphosphonic acid (BPA), (3-bromopropyl)phosphonic acid (BPPA), and (3-aminopropyl)phosphonic acid (APPA), and each μ_OCMFET was measured at 0.73, 0.41, 0.34, and 0.15 cm2V-1s-1, respectively. The results could be suggested that the characteristics of each organic SAM intermediate layer, such as the length of the alkyl chain and the type of functionalized end-group, can control the electrical performances of OCMFET devices and be supported to find the optimized fabrication conditions, as an efficient sensing platform device.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.897-899
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• 1999

In this paper, the interfacial dielectric breakdown phenomenon of interface between Epoxy/EPDM (ethylene propylene diene terpolymer) was discussed, which affects stability of insulation system of power delivery devices. Specimen structure was designed by using MAGSOFT's FLUX2D based on the finite elements method. Design concepts is to reduce the effect of charge transport from electrode in the process of breakdown and to have the tangential electrical potential with the Epoxy/EPDM interface. AC interfacial breakdown phenomenon of was investigated by variation of interfacial conditions oil and temperature which are supposed to have influence on the interfacial breakdown strength. Interfacial breakdown strength was improved by spreading oil over interfacial surface. The decreasing ratio of the AC interfacial breakdown strength in non-oiled specimens was increased by the temperature rising and its of oiled specimens was not affected by temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.276-276
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• 2012

The interface morphology of organic active layers is known to play a crucial role in the performance of organic photovoltaic (OPV) cells. Especially, a controlled nanostructure with a large contact area between electron donor (D) and acceptor (A) layers is necessary to improve the power conversion efficiency (PCE) of the cells since the short exciton diffusion lengths in organic semiconductors limit the charge (hole and electron) separation before excitons recombination. In this work, we developed simple solvent treating methods to fabricate a nanostructured DA interface and applied them to enhance the PCE of ZnPc/C60 based small molecule OPV cells. Interestingly, it was observed that the solvent treatment on the donor layer prior to the deposition of the acceptor layer resulted in a significant decrease in PCE, which was due to an existence of undesirable voids at the DA interface. Instead, the solvent vapor treatment after the DA bilayer formation led to densely packed and well dispersed DA contacts. Consequently, 3-fold enhancement of PCE as compared to the untreated bilayer cell was accomplished.

• Korean Journal of Materials Research
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• v.27 no.7
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• pp.364-368
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• 2017

We performed temperature dependent current-voltage (I-V) measurements to characterize the electrical properties of $Au/Al_2O_3/n-Ge$ metal-insulator-semiconductor (MIS) diodes prepared with and without $H_2O$ prepulse treatment by atomic layer deposition (ALD). By considering the thickness of the $Al_2O_3$ interlayer, the barrier height for the treated sample was found to be 0.61 eV, similar to those of Au/n-Ge Schottky diodes. The thermionic emission (TE) model with barrier inhomogeneity explained the final state of the treated sample well. Compared to the untreated sample, the treated sample was found to have improved diode characteristics for both forward and reverse bias conditions. These results were associated with the reduction of charge trapping and interface states near the $Ge/Al_2O_3$ interface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.116-119
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• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.150.2-150.2
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• 2013

We elucidate the mechanism of the self-assembled organic layer formation at the organic/metal interface of hexaaza-triphenylene-hexacarbonitrile (HATCN)/Au(111) by first-principles calculations and Lowtemperature scanning tunneling microscope (STM). In this work, we used HATCN to deposit organic material which is well known as an efficient OLED charge generation material. Low-temperature STM measurements revealed that self-assembled hexagonal porous structure is formed at terraces of Au(111). We also found that the hexagonal porous structure has chirality and forms only small (<1000 $nm^2$) phaseseparated chiral domains that can easily change their chiral phase in subsequence STM images at 80 K. To explain the mechanism of these observation, we calculated the molecular-molecular and molecule-surface interaction energies by using density functional theory method. We found that the change of their chiral phase resulted from the competition between the two energies. These results have not only verified our experimental observations, but also revealed the delicate balance between different interactions that caused the self-assembed structures at the surface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.664-674
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• 2016

The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

• Electrical & Electronic Materials
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• v.10 no.3
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• pp.239-246
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• 1997

The ZnO is stabilize dielectric constant over a broad temperature range because its addition makes the relaxation time short. In this study, the composite oxide material (B $a_{0.85}$ $Ca_{0.15}$)Ti $O_{3}$ was mixed by ZnO additive material and the dielectric polarization characteristics was studied. The relative density was over 90[%] at all specimen in the structural characteristics. Among of the specimen, the relative density of (B $a_{0.85}$ $Ca_{0.15}$)Ti $O_{3}$ with ZnO (0.4mol) has a 95[%]. The grain size of composite oxide material with an increasing ZnO increased and it was 1.0[.mu.m]-1.22[.mu.m]. In the electrical characteristics, the charge and discharge current was increased by ZnO addition. The dielectric relaxation time was increased by space charge polarization at above 110[.deg. C] and the dielectric relaxation time was fixed by space charge polarization of para-dielectric layer at below 110[.deg. C]. The dielectric relaxation time was maximum when the grain size was small. The dielectric relaxation time is decreased with an additive material ZnO and interface polarization, existing void at the grain and grain boundary. The remnant polarization is increased and the coercive electric field is decreased by ZnO.

• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.262-267
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• 2006

We proposed a PPLN fabrication setup that measures the voltage and current applied to $LiNbO_3$ in real time during application of a DC electric field. Because the duration for transferring a sufficient electron charge to $LiNbO_3$ increases, we are able to control the electron charge flow transferred to $LiNbO_3$ efficiently. We divided the domain inversion process of PPLN into 5 states: Nucleation (state 1), Spread of the domain inversion region under the electrode(state 2), Accumulation of the electron charge at the insulator/$LiNbO_3$ interface(state 3), Domain inversion under the insulator layer after breakdown(state 4), and Lowering the electric field applied to $LiNbO_3$ (state 5). We have found that the Threshold Point is essential for the domain inversion and that the domain inversion process must be stopped within state 3 for the optimum PPLN. Using these results, we could fabricate a stable and reproducible PPLN efficiently.