• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.135-140
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• 2005

Although it was recently observed that severe fatigue damage was formed in Al or Cu interconnects due to the cyclic temperatures generated by Joule heating of the metal lines by the passage of alternating currents (AC), AC loading frequency effect on the damage evolution characteristics are not known so far. This work focused on the effect of AC loading frequency (100 Hz vs. 10 kHz) on the thermo-mechanical fatigue characteristics by using polycrystalline sputtered Cu lines with temperature cycles with amplitudes from 100 to $300^{\circ}C$. It was consistently observed that higher loading frequency accelerated damaged grain growth and led to earlier failure irrespective of Cu grain sizes. The frequency effect is believed to result from differences in the concentration of defects created by the deformation-induced motion of dislocations to the grain boundaries.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.209-215
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• 2001

In this paper a method for analysis and modelling of coplanar transmission interconnect lines that are placed on top of silicon-silicon oxide substrates is presented. The potential function is expressed by series expansions in terms of solutions of the Laplace equation for each homogeneous region of layered structure. The expansion coefficients of different series are related to each other and to potentials applied to the conductors via boundary conditions. In the plane of conductors, boundary conditions are satisfied at $N_d$ discrete points with $N_d$ being equal to the number of terms in the series expansions. The resulting system of inhomogeneous linear equations is solved by matrix inversion. No iterations are required. A discussion of the calculated line admittance parameters as functions of width of conductors, thickness of the layers, and frequency is given. The interconnect capacitance and conductance per unit length results are given and compared with those obtained using full wave solutions, and good agreement have been obtained in all the cases treated

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.9-17
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• 2011

As semiconductor process rapidly developed, the density of chips becomes higher and the space between adjacent lines narrows smaller. This trend increases the capacitance and inductance in interconnects and the coupling-capacitance of adjacent lines grows even bigger than the self-capacitance of themselves, especially in global interconnects. Inductive and capacitive coupling observed in these phenomena may cause serious problems in signal integrity. This paper proposes a codeword generation technique using extra interconnect lines to reduce the crosstalk caused by inductive and capacitive coupling and to reduce dynamic power consumption considering probability of input data. To estimate the performance of the proposed technique, the experimental results have been obtained using FastCap, FastHenry and HSPICE, and it has been shown that the power consumption using the proposed technique has yielded approximately 15% less than the results of the previous technique.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1638-1643
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• 2010

HVDC is better economic method than HVAC in case of long distance transmission and it is possible to interconnect transmission lines regardless of difference of power frequency. The electrical environment problems of HVDC overhead transmission line are electric field, charged voltage, ion current and so on. For biopolar HVDC lines, most of the ions are directed toward the opposite polarity conductor, but a significant fraction is also directed toward the ground. These problems are major factor to design configuration of HVDC overhead transmission line. Therefore, It is necessary to test an environmental characteristics of HVDC overhead transmission line. In this paper, to assess the ion characteristic of HVDC transmission line, continuous measurements have been done on the biopolar single circuit line with ACSR 480mm2-6 bundle conductors of Gochang HVDC Test line. And then the ion characteristics were analyzed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.88-93
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• 2004

We, for the first time, present novel test patterns and conclusive on-chip data indicating that the variation of coupling capacitance, ${\Delta}C_C$ by crosstalk can be larger than static coupling capacitance, $C_C$. The test chip is fabricated using a generic 150 nm CMOS technology with 7 level metallization. It is also shown that ${\Delta}C_C$ is strongly dependent on the phase of aggressive lines. For antiphase crosstalk ${\Delta}C_C$ is always larger than $C_C$ while for in-phase crosstalk $D_{\Delta}C_C$is smaller than $C_C$.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.279-282
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• 2000

As digital systems continue to use components with faster edge rates and clock speeds, transmission of the digital information in these systems approaches the microwave realm. At these speeds digital signal fidelity becomes both a critical success factor and design challenge. The noise sources in digital systems include the noise in power supply, ground and packaging media due to simultaneous switching of drivers, signal reflections and distortions on single and multiple transmission lines. This paper presents theory, case studies and design considerations of gigabit interconnection for network and communication systems. The case studies show HSPICE and Ampredictor simulations of alternate approaches. Various subjects including skin effect and dielectric losses, interconnect simulations and crosstalks of connector, affected signal discontinuity, are addressed.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.445-446
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• 2008

With the semiconductor industry evolving into the deep sub-micron (DSM) era, the crosstalk effects on interconnect lines of a chip have increasingly caused a major bottleneck for design closure. In this paper, we propose an effective design guide line to reduce cell area overhead without crosstalk noise violations by using crosstalk prevention flow with clock shielding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.12-20
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• 1997

Physical interconnect such as Printed Circuit Board(PCB) traces introduces new challenges for parameter extraction and delay calculation for high-speed system design. PCB traces are dominated by frequency dependent LC propagation which makes precharacterization difficult for all possible configurations. Moreover, simulating the transient behavior of the trace for noise and delay analysis requries the combined used of a variety of models and techniques for efficiently handling lossy, low-loss, frequency dependent, and coupled transmission lines together with lumped elements. In this paper we explain how the frequency dependence caused by ground plane proximity and skin effects can be modeled using the adstracted models. These abstracted (lumped) models are SPICE-compatible and can be simulated in time-domain, along with precharacterized lumped parasitic elements and nonlinear driver and load models.