• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.35-42
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• 2010

In this study, crosstalk between dominant interconnect pairs in an A/D converter circuit is analyzed in frequency domain and effects of termination conditions on crosstalk are described, based on the practical circuit conditions. An A/D converter circuit is a mixed circuit where both clean and noisy signals coexist such that the circuit probably suffers from distortion by crosstalk. An analog input signal and the reference voltage signal, which dominate the overall conversion performance of the A/D converter circuit, are ready to be distorted by crosstalk and include specific termination conditions, such as non-matching and capacitive termination, respectively. Thus, this study presents the model of crosstalk considering impedance mismatch at both ends and analyzes effects of the practical termination conditions in the analog input and the reference voltage interconnects on crosstalk. A typical circuit configuration of the two interconnects is described and crosstalk including near-end and far-end termination impedances is modeled. Effects of the near-end impedance mismatch in the analog input interconnect and the far-end capacitive termination in the reference voltage interconnect are estimated in the frequency domain by using the model of crosstalk and experiments are performed to confirm the estimated results. Microstrip lines are used as interconnects, involving the increase of loss in high frequencies.

• Transactions of the Korean hydrogen and new energy society
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• v.21 no.3
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• pp.201-206
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• 2010

In present work, $La_{0.8}Ca_{0.2}CrO_3$ (LCC) ceramic interconnect layer for SOFC was prepared by using thermal plasma spray coating process. The LCC powders were synthesized by Pechini method and calcined at the temperature of $1000^{\circ}C$. The prepared LCC powder was characterized by x-ray diffraction (XRD), scanning electron microscopy (SEM), particle counter, BET analysis, respectively. In addition, basic and essential properties of LCC layer coated by thermal plasma spray coating process such as the morphology of surface and cross section for coated layer, gas leak rate, and electrical conductivity were analyzed and discussed. Based on these experimental results, it can be concluded that the LCC layer coated by thermal plasma spray coating process can be suitable as a ceramic interconnect of SOFC operated at $800^{\circ}C$.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2005.10a
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• pp.283-288
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• 2005

Application of semiconductor sensors has widely spreaded into various industries because those have several merits like easy miniaturization and batch production comparison with previous mechanical sensors. But external conditions such as thermal and repetitive load have a bad effect on sensors's lifetime. Especially, this paper was focused on fatigue life of a interconnect made by various materials. Firstly we implemented the stress analysis for interconnect under thermal load and wording pressure. And the fatigue lifetime of each material was induced by Manson & Coffin Equation using the plastic stress-strain curve obtained by the plastic-elastic Finite Element Analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.71-76
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• 2007

The effect of crosstalk errors is most significant in high-performance circuits. This paper presents effective test patterns for SoC and Board level interconnects considering actual effective aggressors. Initially '6n' algorithm, where 'n' is the total number of interconnect nets, is analyzed to detect and diagnose 100% crosstalk faults. Then, more efficient algorithm is proposed reducing the number of test patterns significantly while maintaining complete crosstalk fault coverage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.20-28
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• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.1024-1030
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• 1999

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 UpdateDR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2 log(n+2) 의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.Abstract IEEE 1149.1 Boundary-Scan is a testable design technique for the detection and diagnosis of faults on a board. However, since it takes 2.5TCKs to observe data launched from an output boundary scan cell due to inherent characteristics of the TAP controller, it is impossible to test delay defects on the interconnect nets. This paper introduces a new technique that postpones the activation of UpdateDR signal by 1.5 TCKs while complying with IEEE 1149.1 standard. Furthermore we have developed 2 log(n+2) , where N is the number of nets, interconnect test patterns to test delay faults in addition to the static interconnect faults. The validness of our approach is verified through the design and simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.